公开(公告)号：US3670304A

公开(公告)日：1972-06-13

申请号：US3670304D

申请日：1970-09-28

Applicant: IBM

Inventor： ANDRESEN ROLF ,  FIORINO BENJAMIN C ,  NICCORE FRED W

IPC: G11B20/18 ,  H04L27/08 ,  G06K5/00

CPC classification number: H04L27/08 ,  G11B20/18

Abstract: A data signal read from magnetic tape is converted from an analog signal into a digital signal by hard limiting. This hardlimited data signal is combined with an indication as to whether the amplitude of the digital signal is above a predetermined threshold and then passed to the control unit operating with the tape drive. The control unit, in turn, detects the data, checks for parity error, phase error, and amplitude error and provides control signals back to the tape drive. These control signals are used to change the predetermined threshold used by the tape drive. The predetermined threshold is changed by these control signals in accordance with detection of a history of good data and in accordance with errors in the record block.

Abstract translation: 从磁带读取的数据信号通过硬限制从模拟信号转换成数字信号。 该硬限制数据信号与数字信号的振幅是否高于预定阈值的指示组合，然后传送到与磁带驱动器一起操作的控制单元。 控制单元依次检测数据，检查奇偶校验错误，相位误差和振幅误差，并将控制信号提供回磁带驱动器。 这些控制信号用于改变磁带驱动器使用的预定阈值。 根据检测到良好数据的历史并根据记录块中的错误，这些控制信号改变预定阈值。

公开(公告)号：CA948284A

公开(公告)日：1974-05-28

申请号：CA134681

申请日：1972-02-14

Applicant: IBM

Inventor： LAURICH LAWRENCE A ,  NICCORE FRED W ,  HOROWITZ ISAAC

IPC: H03L7/099 ,  H04L7/033

Abstract: 1327001 Automatic frequency and phase control systems INTERNATIONAL BUSINESS MACHINES CORP 6 Jan 1972 [16 Feb 1971] 553/72 Addition to 1279026 Heading H3A A digital system for synchronizing a clock signal with a received data signal comprises: means for detecting the phase error between the received data signal and a signal produced by a counter to generate a digital phase correction signal; further means for generating a digital frequency correction signal; and means for adjusting the start and stop of the counter in response to the two correction signals. Counter 12 counts symmetrically from a negative value to a positive value, and passes through zero at the instant when a data pulse should arrive on line DATA REC'D. The count at the actual instant of arrival of a data pulse is an indication of the phase error, and is recorded in register 42. Gates 56 are then suitably enabled to add the previous phase and the new phase error in ADDER 54 and the sum is divided by 2 at 64 to produce an average phase error which is stored in register 62. Gates 56 are then enabled to add the new phase error to the count in frequency register 60, and finally the new phase error is written into register 58 ready for deriving the average phase error during the next cycle of operation. The phase and frequency correction signals thus obtained are weighted by suitable scaling factors in circuits 66, 68 and are fed back on lines 70, 74 to control the start and stop times of counter 12.

公开(公告)号：CA944067A

公开(公告)日：1974-03-19

申请号：CA122731

申请日：1971-09-14

Applicant: IBM

Inventor： ANDRESEN ROLF ,  FIORINO BENJAMIN C ,  NICCORE FRED W

IPC: G11B20/18 ,  H04L27/08

Abstract: A data signal read from magnetic tape is converted from an analog signal into a digital signal by hard limiting. This hard-limited data signal is combined with an indication as to whether the amplitude of the digital signal is above a predetermined threshold and then passed to the control unit operating with the tape drive. The control unit, in turn, detects the data, checks for parity error, phase error, and amplitude error and provides control signals back to the tape drive. These control signals are used to change the predetermined threshold used by the tape drive. The predetermined threshold is changed by these control signals in accordance with detection of a history of good data and in accordance with errors in the record block.