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公开(公告)号:DE3681994D1
公开(公告)日:1991-11-21
申请号:DE3681994
申请日:1986-07-15
Applicant: IBM
IPC: H01L21/302 , C03C15/00 , H01L21/28 , H01L21/3065 , H01L21/311 , H01L21/60 , H01L21/31
Abstract: A process is disclosed for simultaneously etching holes in both the thick and thin portions (20, 21) of a dielectric layer on a semiconductor substrate (19). An anisotropic dry etchant is used to eliminate any significant lateral etching of the dielectric layer (28, 27) during etching. Thus, a mask-and-etch cycle may be eliminated from processing during integrated circuit manufacture, yet dimensional tolerances are maintained.