中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

12 records (took 0.016 seconds)

    3.
    发明专利
    未知

    公开(公告)号：DE69226328D1

    公开(公告)日：1998-08-27

    申请号：DE69226328

    申请日：1992-10-09

    Applicant: IBM

    Inventor： COTE DONNA RIZZONE ,  STANASOLOVICH DAVID ,  WARREN RONALD ARCHER

    IPC: H01L21/28 ,  H01L21/3105 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L29/78

    Abstract: A contact stud for a semiconductor structure is fabricated by providing a semiconductor substrate having a capped region (18) whose sidewall (24) is to be contacted and the method for making the same. The method includes the steps of forming a sidewall spacer (28) contiguous with the said region depositing an insulating layer (34) contiguous with the sidewall spacer so as to insulate the said region and spacer adjacent thereto, etching the sidewall spacer (28) selectively to the cap (20) and the insulating layer (34) for forming a lateral contact window opening (40) for allowing access to the said region, and filling the said contact window opening with a conductive material so as to laterally contact the region (18) for forming the desired stud (42).

    5.
    发明专利
    未知

    公开(公告)号：DE3580796D1

    公开(公告)日：1991-01-17

    申请号：DE3580796

    申请日：1985-07-01

    Applicant: IBM

    Inventor： MERKLING JR ,  STANASOLOVICH DAVID

    IPC: H01L21/302 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/312 ,  H01L21/3213 ,  H01L21/31

    Abstract: A reactive ion etching technique is disclosed for etching a gate electrode out of layers of tungsten silicide (18) and polycrystalline silicon (16) without etching the underlying layer of silicon dioxide (14) which serves as the gate dielectric and which covers the source and drain regions. The key feature of the invention, wherein the gate, which has been partially etched out of the tungsten silicide and polycrystalline silicon layers, is coated with poly tetrafluoroethylene (teflon) (30) to protect the sidewalls (24) of the gate from being excessively etched in the lateral direction while the etching continues at the bottom on either side of the gate.The process is especially suitable for formation of tungsten silicide structures since no subsequent thermal steps are required which would otherwise cause a delamination of the tungsten silicide. In addition to eliminating undercutting, the proess does not disturb the gate oxide over the source and drain areas. which would otherwise create a leaky device unsuitable for applications such as dynamic RAMs. The entire process can be carried out in a single pump down and therefore contamination levels can be minimized.

    8.
    发明专利
    未知

    公开(公告)号：DE69226328T2

    公开(公告)日：1999-03-25

    申请号：DE69226328

    申请日：1992-10-09

    Applicant: IBM

    Inventor： COTE DONNA RIZZONE ,  STANASOLOVICH DAVID ,  WARREN RONALD ARCHER

    IPC: H01L21/28 ,  H01L21/3105 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L29/78

    Abstract: A contact stud for a semiconductor structure is fabricated by providing a semiconductor substrate having a capped region (18) whose sidewall (24) is to be contacted and the method for making the same. The method includes the steps of forming a sidewall spacer (28) contiguous with the said region depositing an insulating layer (34) contiguous with the sidewall spacer so as to insulate the said region and spacer adjacent thereto, etching the sidewall spacer (28) selectively to the cap (20) and the insulating layer (34) for forming a lateral contact window opening (40) for allowing access to the said region, and filling the said contact window opening with a conductive material so as to laterally contact the region (18) for forming the desired stud (42).

    10.
    发明专利
    未知

    公开(公告)号：DE3780743T2

    公开(公告)日：1993-03-11

    申请号：DE3780743

    申请日：1987-09-22

    Applicant: IBM

    Inventor： NANDA MADAN MOHAN ,  PETERMAN STEVEN LOUIS ,  STANASOLOVICH DAVID

    IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L21/31 ,  H01L21/60

    Abstract: A process for defining vias through a polyimide and silicon nitride layer: 1. Providing a substrate having a first layer of silicon nitride and a second layer of polyimide; 2. Depositing a layer of photoresist capable of producing negatively sloped walls; 3. Lithographically defining a pattern of vias in the photoresist; 4. Developing the photoresist to produce a pattern of vias having negatively sloped walls; 5. Etching the polyimide layer using the developed photoresist layer as an etch mask with a CF4/O2 gas mixture; and 6. Etching the silicon nitride layer using the etched polyimide layer as an etch mask with a CF4/H2 gas mixture. y

Patent Agency Ranking