公开(公告)号：DE3463980D1

公开(公告)日：1987-07-02

申请号：DE3463980

申请日：1984-06-20

Applicant: IBM

Inventor： NORGREN KENT STEVEN ,  VOGELSBERG ROBERT ERIC

IPC: G06F13/37 ,  G06F13/36

Abstract: Independent asynchronous bus master devices share a common bus with control lines serially connecting each bus master in a daisy-chain configuration. A Bus Acknowledge signal (34) is received by a local bus master which is thereby enabled (31, 33) to seize control of the bus without an input synchronization delay by first inhibiting (signal 40) synchronization means (41, 41 A, 42, 43) to prevent the passage of the Bus Acknowledge signal (34) to a downstream device for a period of time sufficient to stabilize a Bus Acknowledge Pass signal (44) indicating such passage. In that manner, the Bus Acknowledge signal (44) may be used to control the immediate enabling of local bus seizure thereby avoiding local synchronization delay.

公开(公告)号：DE3484218D1

公开(公告)日：1991-04-11

申请号：DE3484218

申请日：1984-09-10

Applicant: IBM

Inventor： FINLAY DAVID ERNEST ,  NORGREN KENT STEVEN ,  SHOOK FRANKIE SHERWOOD

IPC: G06F13/42 ,  G06F13/16

Abstract: An interface circuit for connecting a memory controller (208) to either a synchronous bus or an asynchronous bus. The interface circuit comprises switch means (197) for supplying a signal indicative of the type of bus and synchronizing means (198) for synchronizing memory access request signals with a local clock when the interface circuit is coupled to an asynchronous bus. An interface method of connecting memory circuits to either a synchronous bus or an asynchronous bus. The method comprises the generation of a mode signal indicative of the type of bus, and the synchronization of the memory access request signals with a local clock when the mode signals indicate an asynchronous bus.

公开(公告)号：DE3176857D1

公开(公告)日：1988-09-29

申请号：DE3176857

申请日：1981-10-29

Applicant: IBM

Inventor： NORGREN KENT STEVEN ,  VOGELSBERG ROBERT ERIC ,  BUSHAW KENNETH ALLEN ,  WOODWARD MILTON HOLLOWAY ,  RACKLEY DARWIN PRESTON

IPC: G06F12/02 ,  G06F13/12 ,  G06F13/18

公开(公告)号：DE3166286D1

公开(公告)日：1984-10-31

申请号：DE3166286

申请日：1981-06-03

Applicant: IBM

Inventor： NORGREN KENT STEVEN ,  STUCKA STEPHEN EDWARD

IPC: H03K19/0175 ,  G06F3/00 ,  H03K17/66 ,  H04L5/16 ,  H03K19/08

Abstract: An electronic switching circut for sequencing asynchronously the direction-indicating signal and the gating signal to a bi-directional switch so that the direction-indicating signal is maintained before, during, and after the gating signal. Provision is made for producing two gating signals in response to a change in the direction of transmission through the bidirectional switch if the direction-indicating signal changes during the gating signal.