公开(公告)号：AU7747881A

公开(公告)日：1982-07-08

申请号：AU7747881

申请日：1981-11-13

Applicant: IBM

Inventor： BUSHAW KENNETH ALLEN ,  BRANSON WILLIAM IRVIN ,  REHAGE TED ANTHONY ,  SHOOK FRANKIE SHERWOOD

IPC: H04N1/00 ,  G06F13/12 ,  H04L29/00 ,  H04N1/32 ,  H04N1/40 ,  G06F3/00

Abstract: An electronic document distribution terminal includes a first adapter (12) coupled to data entry and document preparation means and a second adapter (15) coupled to data transmission means for communication, for example, with a similar terminal. Each of the adapters includes a processor for processing the data received from or for application to a coupled device. A peripheral processing memory (16) is employed to store data to be transferred between the adapters. This memory is under the control of a peripheral processing controller (10) which allocates memory blocks to the adapters under the control of CPU 20. Thus each adapter operates as a stand-alone unit sharing a common memory with the CPU and peripheral processing controller performing only system control functions.

公开(公告)号：AU539142B2

公开(公告)日：1984-09-13

申请号：AU7747881

申请日：1981-11-13

Applicant: IBM

Inventor： BUSHAW KENNETH ALLEN ,  BRANSON WILLIAM IRVIN ,  REHAGE TED ANTHONY ,  SHOOK FRANKIE SHERWOOD

IPC: H04N1/00 ,  G06F13/12 ,  H04L29/00 ,  H04N1/32 ,  H04N1/40 ,  G06F3/00

Abstract: An electronic document distribution terminal includes a first adapter (12) coupled to data entry and document preparation means and a second adapter (15) coupled to data transmission means for communication, for example, with a similar terminal. Each of the adapters includes a processor for processing the data received from or for application to a coupled device. A peripheral processing memory (16) is employed to store data to be transferred between the adapters. This memory is under the control of a peripheral processing controller (10) which allocates memory blocks to the adapters under the control of CPU 20. Thus each adapter operates as a stand-alone unit sharing a common memory with the CPU and peripheral processing controller performing only system control functions.

公开(公告)号：DE3064204D1

公开(公告)日：1983-08-25

申请号：DE3064204

申请日：1980-04-10

Applicant: IBM

Inventor： BIGELOW GEORGE ANDREW ,  REHAGE TED ANTHONY ,  SHOOK FRANKIE SHERWOOD

IPC: G06F3/06 ,  G06F5/06 ,  G06F5/16 ,  G06F13/00 ,  G06F13/38 ,  G11C9/00

公开(公告)号：DE3484218D1

公开(公告)日：1991-04-11

申请号：DE3484218

申请日：1984-09-10

Applicant: IBM

Inventor： FINLAY DAVID ERNEST ,  NORGREN KENT STEVEN ,  SHOOK FRANKIE SHERWOOD

IPC: G06F13/42 ,  G06F13/16

Abstract: An interface circuit for connecting a memory controller (208) to either a synchronous bus or an asynchronous bus. The interface circuit comprises switch means (197) for supplying a signal indicative of the type of bus and synchronizing means (198) for synchronizing memory access request signals with a local clock when the interface circuit is coupled to an asynchronous bus. An interface method of connecting memory circuits to either a synchronous bus or an asynchronous bus. The method comprises the generation of a mode signal indicative of the type of bus, and the synchronization of the memory access request signals with a local clock when the mode signals indicate an asynchronous bus.

公开(公告)号：DE3176841D1

公开(公告)日：1988-09-15

申请号：DE3176841

申请日：1981-10-27

Applicant: IBM

Inventor： BUSHAW KENNETH ALLEN ,  BRANSON WILLIAM IRVIN ,  REHAGE TED ANTHONY ,  SHOOK FRANKIE SHERWOOD

IPC: H04N1/00 ,  G06F13/12 ,  H04L29/00 ,  H04N1/32 ,  H04N1/40 ,  G06F15/16

Abstract: An electronic document distribution terminal includes a first adapter (12) coupled to data entry and document preparation means and a second adapter (15) coupled to data transmission means for communication, for example, with a similar terminal. Each of the adapters includes a processor for processing the data received from or for application to a coupled device. A peripheral processing memory (16) is employed to store data to be transferred between the adapters. This memory is under the control of a peripheral processing controller (10) which allocates memory blocks to the adapters under the control of CPU 20. Thus each adapter operates as a stand-alone unit sharing a common memory with the CPU and peripheral processing controller performing only system control functions.