公开(公告)号：JPS62146035A

公开(公告)日：1987-06-30

申请号：JP26681486

申请日：1986-11-11

Applicant: IBM

Inventor： NORMAN VERNON R ,  SCHRUM JR SIDNEY B ,  WICKER CHARLES R

IPC: H04L7/00 ,  G06F5/12 ,  H04J3/06 ,  H04M7/00

公开(公告)号：JP2007121288A

公开(公告)日：2007-05-17

申请号：JP2006284420

申请日：2006-10-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CRANFORD HAYDEN C JR ,  STEVEN M CLEMENTS ,  WILLIAM P CORNWELL ,  CARRIE E COX ,  NORMAN VERNON R

IPC: G01R35/00 ,  H03K19/00 ,  H03K19/0175

CPC classification number: G01R35/007 ,  Y10T29/49004 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T29/49174

Abstract: PROBLEM TO BE SOLVED: To essentially and accurately calibrate the output impedance of an apparatus to be inspected (DUT) within a prescribed range of allowable impedance. SOLUTION: The DUT is a portion of a source serial termination (SST) serial link transmitter. In the transmitter, two branches of parallel transistors provide an impedance value when a specific transistor of parallel branches is turned on each. The impedance value is added to serially connected resistors to provide output impedance. The DUT comprises a branch of the parallel transistors in series with the resistor. The output impedance of the DUT is compared with the resistance of a reference resistor, and a comparator provides a control signal depending upon whether the output impedance falls within preset percentage fluctuation in the reference resistor. The control signal is processed by an FSM (finite state machine) so that transistors in parallel branches are turned on or off individually so that the DUT impedance value falls within a desired range. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：基本上和精确地校准在允许阻抗的规定范围内待检查装置（DUT）的输出阻抗。

解决方案：DUT是源串行终端（SST）串行链路发射机的一部分。 在发射机中，当并联分支的特定晶体管接通时，并联晶体管的两个分支提供阻抗值。 将阻抗值加到串联的电阻上，以提供输出阻抗。 DUT包括与电阻器串联的并联晶体管的分支。 将DUT的输出阻抗与参考电阻的电阻进行比较，并且比较器根据输出阻抗是否落在参考电阻器的预设百分比波动范围内提供控制信号。 控制信号由FSM（有限状态机）处理，使得并联分支中的晶体管分别导通或截止，使得DUT阻抗值落在所需范围内。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：WO2004015869A8

公开(公告)日：2004-04-22

申请号：PCT/IB0302918

申请日：2003-06-27

Applicant: IBM ,  CRANFORD JR HAYDEN C ,  NORMAN VERNON R ,  SCHMATZ MARTIN

Inventor： CRANFORD JR HAYDEN C ,  NORMAN VERNON R ,  SCHMATZ MARTIN

IPC: H03L7/089 ,  H03L7/10 ,  H03L7/085

CPC classification number: H03L7/10 ,  H03L7/0891 ,  H03L2207/06

Abstract: A phase locked loop circuit for generating a frequency-controlled output signal and a method for providing a frequency controlled output signal in a phase locked loop circuit are introduced. A controllable oscillator unit (260, 460) of said phase locked loop is operated for generating the output signal (261, 461). A frequency of said output signal (261, 461) is evoked by providing the oscillator unit (260, 460) with a first control signal (281, 381, 481) and with a second control signal (241, 341, 441). The first control signal (281, 381, 481) and the second control signal (241, 341, 441) are adapted automatically such that a given reference frequency is achieved in the output signal (261, 461).

Abstract translation: 引入了用于生成频率控制的输出信号的锁相环电路和用于在锁相环电路中提供频率控制的输出信号的方法。 所述锁相环的可控制的振荡器单元（260,460）被操作用于生成输出信号（261,461）。 通过向振荡器单元（260,460）提供第一控制信号（281,381,481）和第二控制信号（241,341,441）来引起所述输出信号（261,461）的频率。 第一控制信号（281,381,481）和第二控制信号（241,341,441）被自动调整，使得在输出信号（261,461）中实现给定的参考频率。

公开(公告)号：AU2003244959A1

公开(公告)日：2004-02-25

申请号：AU2003244959

申请日：2003-06-27

Applicant: IBM

Inventor： NORMAN VERNON R ,  SCHMATZ MARTIN ,  CRANFORD HAYDEN C JR

IPC: H03L7/089 ,  H03L7/10 ,  H03L7/085

Abstract: A phase locked loop circuit for generating a frequency-controlled output signal and a method for providing a frequency controlled output signal in a phase locked loop circuit are introduced. A controllable oscillator unit (260, 460) of said phase locked loop is operated for generating the output signal (261, 461). A frequency of said output signal (261, 461) is evoked by providing the oscillator unit (260, 460) with a first control signal (281, 381, 481) and with a second control signal (241, 341, 441). The first control signal (281, 381, 481) and the second control signal (241, 341, 441) are adapted automatically such that a given reference frequency is achieved in the output signal (261, 461).