公开(公告)号：DE68919376D1

公开(公告)日：1994-12-22

申请号：DE68919376

申请日：1989-02-28

Applicant: IBM

Inventor： MOSLEY JOSEPH MICHAEL ,  MULLGRAV ALLAN LESLIE JR ,  NOTO PHILIP KRANKIE ,  PETERSON CLARENCE IVAN ,  CULICAN EDWARD FRANCIS ,  DAVIS JOHN DONALD ,  EWEN JOHN FARLEY ,  MCCABE SCOTT ALLAN ,  PRITZLAFF PHILIPP EDWARD

IPC: H01L21/822 ,  H01L21/82 ,  H01L27/04 ,  H01L27/118 ,  H03K19/003 ,  H03L7/07 ,  H03L7/099 ,  H03L7/23 ,  H03L7/22 ,  H03L7/06

Abstract: A single logic gate array chip (1) is disclosed having a first portion (2) dedicated to the generation of one or more clock signals and the remaining portion (3) occupied by logic circuits. The first portion (2) uses the same gate array cell design as embodied in the logic circuits of the remaining portion (3). Both portions are powered by similar gate array metallization patterns, although some of the cells of the clock signal sources are disconnected from the normal chip powering busses and are powered instead by respective control signal generators. Each control signal represents the frequency difference between a given clock signal and a reference signal. The cells which are powered by a given control signal introduce a commensurate signal delay to drive the clock signal frequency into a predetermined relationship with the frequency of the reference signal.

公开(公告)号：DE68919376T2

公开(公告)日：1995-05-24

申请号：DE68919376

申请日：1989-02-28

Applicant: IBM

Inventor： MOSLEY JOSEPH MICHAEL ,  MULLGRAV ALLAN LESLIE JR ,  NOTO PHILIP KRANKIE ,  PETERSON CLARENCE IVAN ,  CULICAN EDWARD FRANCIS ,  DAVIS JOHN DONALD ,  EWEN JOHN FARLEY ,  MCCABE SCOTT ALLAN ,  PRITZLAFF PHILIPP EDWARD

IPC: H01L21/822 ,  H01L21/82 ,  H01L27/04 ,  H01L27/118 ,  H03K19/003 ,  H03L7/07 ,  H03L7/099 ,  H03L7/23 ,  H03L7/22 ,  H03L7/06

Abstract: A single logic gate array chip (1) is disclosed having a first portion (2) dedicated to the generation of one or more clock signals and the remaining portion (3) occupied by logic circuits. The first portion (2) uses the same gate array cell design as embodied in the logic circuits of the remaining portion (3). Both portions are powered by similar gate array metallization patterns, although some of the cells of the clock signal sources are disconnected from the normal chip powering busses and are powered instead by respective control signal generators. Each control signal represents the frequency difference between a given clock signal and a reference signal. The cells which are powered by a given control signal introduce a commensurate signal delay to drive the clock signal frequency into a predetermined relationship with the frequency of the reference signal.

公开(公告)号：ES2064477T3

公开(公告)日：1995-02-01

申请号：ES89480033

申请日：1989-02-28

Applicant: IBM

Inventor： MOSLEY JOSEPH MICHAEL ,  MULLGRAV ALLAN LESLIE JR ,  NOTO PHILIP KRANKIE ,  PETERSON CLARENCE IVAN JR ,  CULICAN EDWARD FRANCIS SR ,  DAVIS JOHN DONALD ,  EWEN JOHN FARLEY ,  MCCABE SCOTT ALLAN ,  PRITZLAFF PHILIPP EDWARD JR

IPC: H01L21/822 ,  H01L21/82 ,  H01L27/04 ,  H01L27/118 ,  H03K19/003 ,  H03L7/07 ,  H03L7/099 ,  H03L7/23 ,  H03L7/22 ,  H03L7/06

Abstract: A single logic gate array chip (1) is disclosed having a first portion (2) dedicated to the generation of one or more clock signals and the remaining portion (3) occupied by logic circuits. The first portion (2) uses the same gate array cell design as embodied in the logic circuits of the remaining portion (3). Both portions are powered by similar gate array metallization patterns, although some of the cells of the clock signal sources are disconnected from the normal chip powering busses and are powered instead by respective control signal generators. Each control signal represents the frequency difference between a given clock signal and a reference signal. The cells which are powered by a given control signal introduce a commensurate signal delay to drive the clock signal frequency into a predetermined relationship with the frequency of the reference signal.