公开(公告)号：DE3577022D1

公开(公告)日：1990-05-10

申请号：DE3577022

申请日：1985-11-19

Applicant: IBM

Inventor： CULICAN EDWARD FRANCIS ,  PRITZLAFF JR

IPC: H03K19/013 ,  H01L21/3205 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04 ,  H01L27/118 ,  H03K19/003 ,  H03K19/088 ,  H03K19/173

Abstract: The invention is directed to integrated circuit chips and particularly to "gate array", or "master slices" whereon one or more circuits (IC1...IC5) drive a highly capacitive on-chip wiring (H, IC6) net. The driving circuits are modified and a compensation circuit (CC; R1, T1) coupled to the highly capacitive on-chip wiring net to mitigate the burden caused by the high capacitance. The integrated circuit structure contains, efficiently positioned on each chip, a number of compensation circuits which are readily connectable during the fabrication of the chip. The employment of one, or a number of, on-chip compensation circuits does not materially increase the chip power consumption.

公开(公告)号：DE68919376D1

公开(公告)日：1994-12-22

申请号：DE68919376

申请日：1989-02-28

Applicant: IBM

Inventor： MOSLEY JOSEPH MICHAEL ,  MULLGRAV ALLAN LESLIE JR ,  NOTO PHILIP KRANKIE ,  PETERSON CLARENCE IVAN ,  CULICAN EDWARD FRANCIS ,  DAVIS JOHN DONALD ,  EWEN JOHN FARLEY ,  MCCABE SCOTT ALLAN ,  PRITZLAFF PHILIPP EDWARD

IPC: H01L21/822 ,  H01L21/82 ,  H01L27/04 ,  H01L27/118 ,  H03K19/003 ,  H03L7/07 ,  H03L7/099 ,  H03L7/23 ,  H03L7/22 ,  H03L7/06

Abstract: A single logic gate array chip (1) is disclosed having a first portion (2) dedicated to the generation of one or more clock signals and the remaining portion (3) occupied by logic circuits. The first portion (2) uses the same gate array cell design as embodied in the logic circuits of the remaining portion (3). Both portions are powered by similar gate array metallization patterns, although some of the cells of the clock signal sources are disconnected from the normal chip powering busses and are powered instead by respective control signal generators. Each control signal represents the frequency difference between a given clock signal and a reference signal. The cells which are powered by a given control signal introduce a commensurate signal delay to drive the clock signal frequency into a predetermined relationship with the frequency of the reference signal.

公开(公告)号：DE68919376T2

公开(公告)日：1995-05-24

申请号：DE68919376

申请日：1989-02-28

Applicant: IBM

Inventor： MOSLEY JOSEPH MICHAEL ,  MULLGRAV ALLAN LESLIE JR ,  NOTO PHILIP KRANKIE ,  PETERSON CLARENCE IVAN ,  CULICAN EDWARD FRANCIS ,  DAVIS JOHN DONALD ,  EWEN JOHN FARLEY ,  MCCABE SCOTT ALLAN ,  PRITZLAFF PHILIPP EDWARD

IPC: H01L21/822 ,  H01L21/82 ,  H01L27/04 ,  H01L27/118 ,  H03K19/003 ,  H03L7/07 ,  H03L7/099 ,  H03L7/23 ,  H03L7/22 ,  H03L7/06

Abstract: A single logic gate array chip (1) is disclosed having a first portion (2) dedicated to the generation of one or more clock signals and the remaining portion (3) occupied by logic circuits. The first portion (2) uses the same gate array cell design as embodied in the logic circuits of the remaining portion (3). Both portions are powered by similar gate array metallization patterns, although some of the cells of the clock signal sources are disconnected from the normal chip powering busses and are powered instead by respective control signal generators. Each control signal represents the frequency difference between a given clock signal and a reference signal. The cells which are powered by a given control signal introduce a commensurate signal delay to drive the clock signal frequency into a predetermined relationship with the frequency of the reference signal.

公开(公告)号：IN175608B

公开(公告)日：1995-07-15

申请号：IN558DE1989

申请日：1989-06-27

Applicant: IBM

Inventor： CULICAN EDWARD FRANCIS ,  DAVIS JOHN DONALD ,  EWEN JOHN FARLEY ,  MOCABE SCOTT ALLAN ,  MULLGRAVE JOSEPH MICHAEL MOSLE ,  NOTO PHILIP FRANKIE

IPC: H01L49/00

公开(公告)号：DE3676620D1

公开(公告)日：1991-02-07

申请号：DE3676620

申请日：1986-10-07

Applicant: IBM

Inventor： CULICAN EDWARD FRANCIS ,  PRITZLAFF JR ,  VAN GOOR KENNETH ALAN ,  SCHETTLER HELMUT

IPC: H03K19/0175 ,  H03K17/60 ,  H03K19/013 ,  H03K19/018 ,  H03K19/088 ,  H03K19/082

Abstract: Circuitry for enhancing the ability of digital circuits to drive highly capacitive loads is disclosed. This circuitry has particular utility when employed with logic circuits such as "TTL" (Transistor- Transistor Logic) and "DTL" (Diode-Transistor Logic). … The circuitry (15) comprises four transistors (T1, T2, T3A, T3B) and two resistors (R1, R2), at least one of the transistors (T1, T3A) being connected as a diode.