公开(公告)号：JP2013114397A

公开(公告)日：2013-06-10

申请号：JP2011259178

申请日：2011-11-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

Inventor： TAKANO KOJI ,  OBA NOBUYUKI ,  KATAYAMA YASUNAO

IPC: G06F13/10 ,  G06F12/00

CPC classification number: G06F17/30132

Abstract: PROBLEM TO BE SOLVED: To make control of a receiver and downloading possible by avoiding a problem of a cache by an OS.SOLUTION: A mirror file number corresponding to a file to be requested is transmitted to a host OS. It is determined that whether or not data is cached in the host OS, and a block device is requested to read data of the mirror file number when it is determined that the transmitted data of the mirror file number is not cached. The block device acquires an address in memory in which actual content corresponding to a sector number is stored, acquires a sequence number corresponding to the content, changes the acquired sequence number and read data in the acquired address in the memory. Data obtained by adding the changed sequence number to the read data is provided to the host OS. When it is determined that data is cached in the host OS, the data cached in the host OS is provided.

Abstract translation: 要解决的问题：通过避免OS的高速缓存问题，来使接收机的控制和下载成为可能。 解决方案：将与要请求的文件相对应的镜像文件号码发送到主机OS。 确定数据是否被缓存在主机OS中，并且当确定镜像文件号的发送数据未被高速缓存时，请求块装置读取镜像文件号的数据。 块装置获取存储有对应于扇区号的实际内容的存储器中的地址，获取与内容相对应的序列号，改变所获取的序列号并读取存储器中获取的地址中的数据。 通过将改变的序列号添加到读取的数据而获得的数据被提供给主机OS。 当确定在主机OS中缓存数据时，提供缓存在主机OS中的数据。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2012124668A

公开(公告)日：2012-06-28

申请号：JP2010272709

申请日：2010-12-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： OKAZAKI ATSUYA ,  OBA NOBUYUKI

IPC: H04L12/28 ,  H04L12/44

CPC classification number: H04B10/278 ,  H04Q11/0067 ,  H04Q2011/0064 ,  H04Q2011/0079

Abstract: PROBLEM TO BE SOLVED: To provide a method that arbitrates (arbitration) an access to (use of) an optical communication bus for a node without requiring an expensive WDM device.SOLUTION: A method for arbitrating an access to an optical communication bus includes the following steps: always sending a signal onto a bus for each node (Node A, Node B, Node C and Node D) to synchronize with the signal, thus maintaining a CDR lock state, and for a node desiring to use the bus to emits light as a request bit in a pre-assigned time slot in a frame header being sent on the bus, thereby performing bus arbitration (arbitration); sending data (data) onto the bus when an access right to (use of) the bus is obtained; making each node monitor the states of light emitting; sending an idle pattern (ip) onto the bus at a predetermined timing assigned to the node; and making all nodes send the idle pattern at least once during a pre-assigned period of all the nodes to keep a DC balance of an AC coupling device.

Abstract translation: 要解决的问题：提供一种在不需要昂贵的WDM设备的情况下仲裁（仲裁）访问（使用）用于节点的光通信总线的方法。 解决方案：一种用于仲裁对光通信总线的访问的方法包括以下步骤：总是向每个节点（节点A，节点B，节点C和节点D）向总线发送信号以与该信号同步， 从而保持CDR锁定状态，并且对于希望使用总线发出光的节点作为在总线上发送的帧头中的预分配时隙中的请求位，从而执行总线仲裁（仲裁）; 当获取（使用）总线的访问权限时，将数据（数据）发送到总线上; 使每个节点监视发光的状态; 在分配给该节点的预定定时向总线发送空闲模式（ip）; 并使所有节点在所有节点的预分配周期期间至少发送一次空闲模式，以保持AC耦合设备的DC平衡。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JPH10262041A

公开(公告)日：1998-09-29

申请号：JP5948097

申请日：1997-03-13

Applicant: IBM

Inventor： KOBAYASHI YOSHINAO ,  OBA NOBUYUKI ,  MUNETO SEIJI

IPC: H04L9/08 ,  H04L9/10 ,  H04L9/12

Abstract: PROBLEM TO BE SOLVED: To non-specifically execute the exposure/non-exposure mode of a secret key by outputting a presumable bit string, in response to the input of an initial bit string and performing the switching between the enciphering processing and the output processing of input bit strings, when the output of a prescribed trap bit string is detected. SOLUTION: When an initial bit string is loaded into an LFSR(linear feedback shift register) 1, a trap decoder 3 starts its operation to monitor the bit of the LFSR 1. When a trap bit string is detected, the decoder 3 outputs a switch signal and a toggle switch 5 inverts its own output. Then the output of the LFSR 1 continuously serves as the input of an exclusive OR circuit 19, until the decoder 3 outputs a switch signal. At the same time, the output of a shift register 11a undergoes the exclusive OR processing (enciphering processing) by means of a pseudo-random number, i.e., the output of the LFSR 1. Meanwhile, the output of the register 11a is used as it is, when the decoder 3 outputs a switch signal.

公开(公告)号：JPH0895863A

公开(公告)日：1996-04-12

申请号：JP22161494

申请日：1994-09-16

Applicant: IBM

Inventor： OBA NOBUYUKI ,  NAKADA TAKEO ,  SHO IKUO

IPC: G06F12/08

Abstract: PURPOSE: To provide a method for maintaining consistency of cache in a system which has 1st physical memory and 2nd physical memory that is common with at least a part of physical addresses of all of physical addresses of the 1st physical memory, selects the 1st physical memory/2nd physical memory by its operation mode and accesses. CONSTITUTION: Flag bit 23 is provided as a means which stores information that specifies data source in tag memory 20 of cache. Then, the cache decides cache hit/miss based on not only a fact that the data relating to an CPU request address exists in the cache, but also considers the information on an operation mode which is simultaneoulsy sent from the CPU and also decides whether data source whose data the CPU requests coincides with data source whose data is stored in the cache. The cache hit is not decided until these two conditions are matched with each other.

公开(公告)号：JPH03253963A

公开(公告)日：1991-11-13

申请号：JP3753690

申请日：1990-02-20

Applicant: IBM

Inventor： OBA NOBUYUKI ,  SHIMIZU SHIGENORI

IPC: G06F12/08 ,  G06F15/16 ,  G06F15/177

Abstract: PURPOSE: To improve system performance by providing a means execution data consistency procedure to the data based on the comparing result and state information of a comparing means to reduce the traffic of a shared path. CONSTITUTION: A reference value register 6 stores a reference value in connection with the access count of a cache tag and a comparator 7 compares the access count of a cache tag specified by address information with the reference value of the reference value register 6 to supply the comparing result for a cache control part 3. In this case, with respect to data to which only one processor P frequently access, even though originally shared data, its copy is made to remain only in the cache C of the frequently accessing processor P and its copy within the other caches are invalidated. As the result of the, there is no copy in the other caches C after invalidating so that processing can be executed only within one's own cache C, thereby improving the performance of the bus of the cache to maximum.

公开(公告)号：JP2016004420A

公开(公告)日：2016-01-12

申请号：JP2014124370

申请日：2014-06-17

Applicant: IBM

Inventor： OBA NOBUYUKI ,  MUNETO SEIJI

IPC: G06F12/06 ,  G06F1/32 ,  G06F12/00 ,  G06F12/16

Abstract: 【課題】DRAM及びNVRAMを含む主メモリを備えるコンピュータの動作状態に応じて主メモリを管理するための方法を提供する。【解決手段】その方法は、(a)コンピュータの起動時において、プログラム等をDRAMにロードし、かつ所定のリードオンリーのデータ等をNVRAMにロードすること、(b)通常動作からサスペンド状態への状態遷移において、DRAMのデータをページ単位でNVRAMに移動すること、(c)サスペンド状態から通常動作への状態遷移において、プログラムの実行のためにNVRAMからページ単位でデータを読み出すこと、(d)NVRAMへのページ単位でのデータの書き込みが発生した場合、データの書き込みを停止し、データの書き込みが行われるNVRAMのデータ領域のデータをページ単位でDRAMに移動させること、及び(e)データの移動後のDRAMにおいて、ページ単位でのデータの書き込みを行うことを含む。【選択図】図1

公开(公告)号：JP2012170014A

公开(公告)日：2012-09-06

申请号：JP2011031231

申请日：2011-02-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： OBA NOBUYUKI ,  TAKANO KOJI ,  KATAYAMA YASUNAO

IPC: H04W28/04 ,  H04L29/08

CPC classification number: H04L1/1854 ,  H04L1/1838 ,  H04L1/24 ,  H04W28/04

Abstract: PROBLEM TO BE SOLVED: To download data of a high-capacity file from a server (an access point) to a client (a portable device) of a user at a high speed with efficiently using both millimeter wave wireless communication and the conventional wireless communication (WiFi, Bluetooth (R), 3G, and the like).SOLUTION: File data is packetized and transmitted from a server to a client. The file data is transmitted as a data packet by a millimeter wave. In parallel to that, a check-out packet (a roll-calling packet) corresponding to the data packet is transmitted. At establishment of a link, a latency of each communication channel is measured for testing. On a reception side, when reception of the check-out packet is completed, whether or not a millimeter wave packet corresponding to the check-out packet is arrived is checked (or roll-calling is performed). If no corresponding millimeter wave packet is arrived, it is determined that the corresponding millimeter wave packet is lost, and a retransmission request is returned to the server readily via WiFi.

Abstract translation: 要解决的问题：为了将高容量文件从服务器（接入点）的数据高速地下载到用户的客户机（便携式设备），有效地使用毫米波无线通信和 传统的无线通信（WiFi，蓝牙，3G等）。 解决方案：文件数据被打包并从服务器发送到客户端。 文件数据以毫米波作为数据包发送。 与此并行地，发送对应于数据分组的检出分组（滚动呼叫分组）。 在建立链路时，测量每个通信信道的延迟。 在接收侧，当接收到检出包完成时，检查与检出包相对应的毫米波分组是否被到达（或进行滚动呼叫）。 如果没有相应的毫米波分组到达，则确定对应的毫米波分组丢失，并且通过WiFi容易地将重传请求返回给服务器。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JPH0787094A

公开(公告)日：1995-03-31

申请号：JP20612693

申请日：1993-08-20

Applicant: IBM

Inventor： OBA NOBUYUKI

IPC: G06F13/362 ,  H04L12/931 ,  H04L12/937 ,  H04Q3/00 ,  H04L12/28

Abstract: PURPOSE: To provide a mediation method for accelerating switching in a large- scaled asynchronous transfer mode switch. CONSTITUTION: A cross bar system is adopted, and when two or more output requests turned to the same output port compete, request signals for indicating the output requests for the requests are NAND operated for the respective rows of a matrix with one-bit signals stored beforehand in a matrix shape, the result of the NAND operation is wired OR operated for the respective columns of the matrix and internal signals Q are obtained for the respective columns. It is detected that the order of the internal signals Q is in complimentary relation with the order relating to one row of the one-bit signals stored beforehand in the matrix shape and understanding signals are generated for the output request relating to the row of the equal order. A mediation process is executed at an extremely high speed because it is all performed on a hardware.

公开(公告)号：JP2008299530A

公开(公告)日：2008-12-11

申请号：JP2007143968

申请日：2007-05-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NAKADA TAKEO ,  OBA NOBUYUKI ,  HARADA NOBUYUKI

IPC: G06F12/08 ,  G06F3/06

CPC classification number: G06F12/121 ,  G06F12/0804 ,  G06F2212/1016 ,  G06F2212/2022

Abstract: PROBLEM TO BE SOLVED: To efficiently rewrite data from a cache memory to a main memory. SOLUTION: The storage device for caching data to be written in the main memory includes: a cache memory having a plurality of cache segments in each of which validity data indicating whether each sector included in the cache segment is a valid sector including valid data are stored; and a cache control part for controlling access to the cache memory. In writing back the cache segment to the main memory, the cache control part performs access to validity data corresponding to the cache segment, and detects a region where invalid sectors are continued, and issues a reading command to read the data to every detected region to the main memory, and writes back the data in the cache segment to the main memory after setting each region as a valid sector. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：有效地将数据从高速缓冲存储器重写到主存储器。 解决方案：用于缓存要写入主存储器中的数据的高速缓存存储器包括：具有多个高速缓存段的高速缓冲存储器，每个高速缓存段中的每一个高速缓存段指示包括在高速缓存段中的每个扇区是否包括有效扇区， 数据存储; 以及用于控制对高速缓冲存储器的访问的高速缓存控制部分。 在将高速缓存段写回到主存储器中时，高速缓存控制部分执行与高速缓存段相对应的有效性数据的访问，并且检测到无效扇区继续的区域，并发出读取命令以将数据读取到每个检测到的区域 主存储器，并将每个区域设置为有效扇区后，将高速缓存段中的数据写回主存储器。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2006113696A

公开(公告)日：2006-04-27

申请号：JP2004298264

申请日：2004-10-12

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： TAKANO KOJI ,  OBA NOBUYUKI

IPC: G06F11/22 ,  G01R31/319 ,  G06F11/30

CPC classification number: G01R31/318357 ,  G06F17/5022

Abstract: PROBLEM TO BE SOLVED: To efficiently perform the debug of a logic circuit by detecting an operation whose failure is highly likely to be generated, and reporting it. SOLUTION: This observation device 20 for inputting a signal to be outputted by an observation object device, and for observing the operation of the observation object device is provided with an output signal acquiring part 100 for acquiring an output signal to be outputted by the observation object device 10, status transition storing parts 102a and 102b for storing the set of the output signals acquired in two or more continuous cycles as the status transition of the output signals, status transition adding parts 110a and 110b for, when the status transition corresponding to the set of the output signals newly acquired by the output signal acquiring part 100 is not stored in the status transition storing parts 102a and 102b, making the status transition storing part additionally store the set of the newly acquired output signals as new status transition and a status transition output part 120 for outputting the status transition of the output signals stored in the status transition storing parts 102a and 102b. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：通过检测故障很可能产生的操作并报告来有效地执行逻辑电路的调试。 解决方案：用于输入由观察对象装置输出的信号并且用于观察观察对象装置的操作的观察装置20设置有输出信号获取部100，用于获取要输出的输出信号， 观察对象装置10，状态转换存储部102a，102b，用于将在两个或多个连续周期中获取的输出信号的集合作为输出信号的状态转换，状态转移添加部分110a和110b用于存储状态转换 对应于由输出信号获取部分100新获取的输出信号的集合不存储在状态转变存储部分102a和102b中，使得状态转换存储部分将新获取的输出信号的集合另外存储为新的状态转换 以及状态转换输出部分120，用于输出存储在状态转换中的输出信号的状态转换 存储部分102a和102b。 版权所有（C）2006，JPO＆NCIPI