公开(公告)号：JPH02238553A

公开(公告)日：1990-09-20

申请号：JP5776289

申请日：1989-03-13

Applicant: IBM JAPAN

Inventor： FUKUDA MUNEHIRO ,  MATSUMOTO TAKASHI ,  NAKADA TAKEO

IPC: G06F15/173 ,  G06F9/45 ,  G06F9/52 ,  G06F15/167

Abstract: PURPOSE:To ensure the effective use of a multiprocessor system for plural applications by transmitting the synchronism satisfaction signals to the corresponding processors based on the result of the comparison carried out between the signal received from a synchronizing signal bus and the contents of a synchronous register. CONSTITUTION:The synchronizing signal lines SL1 - SLn of a synchronizing signal bus 2 are assigned to the processors P1 - Pn respectively. Then the syn chronizing signals Sync are transmitted from the processors P1 - Pn. A compara tor 4 samples the data on the bus 2 for each clock or each half clock and compares them with the data on a synchronous register 3. A timing control circuit 5 receives the signals Sync and returns the signals Sync and Ack accord ing to the clocks. Thus it is possible to attain at a high speed many synchronous states among the processes to which the processors P1 - Pn are assigned and to carry out plural parallel processing programs at the same time.

公开(公告)号：CA2011503C

公开(公告)日：1994-03-15

申请号：CA2011503

申请日：1990-03-05

Applicant: IBM

Inventor： FUKUDA MUNEHIRO ,  MATSUMOTO TAKASHI ,  NAKADA TAKEO

IPC: G06F15/173 ,  G06F9/45 ,  G06F9/52 ,  G06F15/167 ,  G06F1/12

Abstract: A number of synchronization controllers are provided for a multiprocessor system, one controller being provided for each processor and all being commonly connected to a synchronization signal bus. Each of these synchronization controllers has a synchronization wait signal transmitting means for receiving a synchronization request signal from a corresponding processor and transmitting a synchronization wait signal to the synchronization signal bus. Each controller also includes: (a) a synchronization register for specifying the other processors to be synchronized with the corresponding processor; (b) a comparator means for comparing the signal from the synchronization signal bus with the content of the synchronization register; and (c) a means for transmitting to the corresponding processor a synchronization-acknowledge signal based on the result of the comparison by the comparator means.

公开(公告)号：JP2008269224A

公开(公告)日：2008-11-06

申请号：JP2007110453

申请日：2007-04-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： HARADA NOBUYUKI ,  NAKADA TAKEO

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0804 ,  G06F12/126 ,  G06F2212/1016 ,  G06F2212/2022

Abstract: PROBLEM TO BE SOLVED: To enhance efficiency of access to a memory with slow write speed.
SOLUTION: A storage device for caching data read from a main memory and data to be written to the main memory comprises a cache memory having a plurality of cache segments, in which one or more cache segments holding data consistent with that in the main memory are protected from being rewritten within a predetermined reference quantity; and a cache control part which assigns, according to a write cache miss, a cache segment selected from the cache segment not protected for caching write data, and writes the data to the selected cache segment.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提高以较慢的写入速度访问存储器的效率。 解决方案：用于缓存从主存储器读取的数据和要写入主存储器的数据的存储设备包括具有多个高速缓存段的高速缓冲存储器段，其中保存数据的一个或多个缓存段与 保护主存储器不被预定参考数量重写; 以及高速缓存控制部分，其根据写入高速缓存未命中分配从未被保护以缓存写入数据的高速缓存段中选择的高速缓存段，并将数据写入所选择的高速缓存段。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JPH0895863A

公开(公告)日：1996-04-12

申请号：JP22161494

申请日：1994-09-16

Applicant: IBM

Inventor： OBA NOBUYUKI ,  NAKADA TAKEO ,  SHO IKUO

IPC: G06F12/08

Abstract: PURPOSE: To provide a method for maintaining consistency of cache in a system which has 1st physical memory and 2nd physical memory that is common with at least a part of physical addresses of all of physical addresses of the 1st physical memory, selects the 1st physical memory/2nd physical memory by its operation mode and accesses. CONSTITUTION: Flag bit 23 is provided as a means which stores information that specifies data source in tag memory 20 of cache. Then, the cache decides cache hit/miss based on not only a fact that the data relating to an CPU request address exists in the cache, but also considers the information on an operation mode which is simultaneoulsy sent from the CPU and also decides whether data source whose data the CPU requests coincides with data source whose data is stored in the cache. The cache hit is not decided until these two conditions are matched with each other.

公开(公告)号：DE69030523D1

公开(公告)日：1997-05-28

申请号：DE69030523

申请日：1990-02-23

Applicant: IBM

Inventor： FUKUDA MUNEHIRO ,  MATSUMOTO TAKASHI ,  NAKADA TAKEO

IPC: G06F15/173 ,  G06F9/45 ,  G06F9/52 ,  G06F15/167 ,  G06F15/16 ,  G06F9/46

Abstract: A multiprocessor system wherein a plurality of processors are connected through a shared data bus, each of the processors generating synchronisation request signals in response to its instruction stream, synchronisation required among processes assigned to the processors being achieved by the synchronisation request signals, wherein indicators signifying the requirement to synchronise are embedded in the processes and there is provided a synchronisation controller to each of the processors; and a synchronisation signal bus to which the synchronisation controllers are commonly connected; and each synchronisation controllers has means for recording which processors are involved in the current process synchronisation, means for broadcasting on the synchronisation bus the current processor status in an individual portion of the communication channel provided thereby, means for snooping the synchronisation bus to monitor the total communication channel and means responsive to such snooping and to the involvement recording means to signal the associated processor that all processors recorded to be involved are indicating the same status. The system can be rendered hierarchical by clustering and can handle pipelined operations.

公开(公告)号：DE69030523T2

公开(公告)日：1997-10-23

申请号：DE69030523

申请日：1990-02-23

Applicant: IBM

Inventor： FUKUDA MUNEHIRO ,  MATSUMOTO TAKASHI ,  NAKADA TAKEO

IPC: G06F15/173 ,  G06F9/45 ,  G06F9/52 ,  G06F15/167 ,  G06F15/16 ,  G06F9/46

Abstract: A multiprocessor system wherein a plurality of processors are connected through a shared data bus, each of the processors generating synchronisation request signals in response to its instruction stream, synchronisation required among processes assigned to the processors being achieved by the synchronisation request signals, wherein indicators signifying the requirement to synchronise are embedded in the processes and there is provided a synchronisation controller to each of the processors; and a synchronisation signal bus to which the synchronisation controllers are commonly connected; and each synchronisation controllers has means for recording which processors are involved in the current process synchronisation, means for broadcasting on the synchronisation bus the current processor status in an individual portion of the communication channel provided thereby, means for snooping the synchronisation bus to monitor the total communication channel and means responsive to such snooping and to the involvement recording means to signal the associated processor that all processors recorded to be involved are indicating the same status. The system can be rendered hierarchical by clustering and can handle pipelined operations.

公开(公告)号：JP2008299530A

公开(公告)日：2008-12-11

申请号：JP2007143968

申请日：2007-05-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NAKADA TAKEO ,  OBA NOBUYUKI ,  HARADA NOBUYUKI

IPC: G06F12/08 ,  G06F3/06

CPC classification number: G06F12/121 ,  G06F12/0804 ,  G06F2212/1016 ,  G06F2212/2022

Abstract: PROBLEM TO BE SOLVED: To efficiently rewrite data from a cache memory to a main memory. SOLUTION: The storage device for caching data to be written in the main memory includes: a cache memory having a plurality of cache segments in each of which validity data indicating whether each sector included in the cache segment is a valid sector including valid data are stored; and a cache control part for controlling access to the cache memory. In writing back the cache segment to the main memory, the cache control part performs access to validity data corresponding to the cache segment, and detects a region where invalid sectors are continued, and issues a reading command to read the data to every detected region to the main memory, and writes back the data in the cache segment to the main memory after setting each region as a valid sector. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：有效地将数据从高速缓冲存储器重写到主存储器。 解决方案：用于缓存要写入主存储器中的数据的高速缓存存储器包括：具有多个高速缓存段的高速缓冲存储器，每个高速缓存段中的每一个高速缓存段指示包括在高速缓存段中的每个扇区是否包括有效扇区， 数据存储; 以及用于控制对高速缓冲存储器的访问的高速缓存控制部分。 在将高速缓存段写回到主存储器中时，高速缓存控制部分执行与高速缓存段相对应的有效性数据的访问，并且检测到无效扇区继续的区域，并发出读取命令以将数据读取到每个检测到的区域 主存储器，并将每个区域设置为有效扇区后，将高速缓存段中的数据写回主存储器。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2010128730A

公开(公告)日：2010-06-10

申请号：JP2008301875

申请日：2008-11-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： TAKANO KOJI ,  OBA NOBUYUKI ,  NAKADA TAKEO

IPC: G06F13/38

Abstract: PROBLEM TO BE SOLVED: To provide a device etc. capable of efficiently performing data transfer when transferring measurement data to be observed to a subsequent stage so that a fatal loss of measurement information is prevented even if the measurement data exceeds a transfer band. SOLUTION: The device includes: (A) a data receiver unit for successively receiving occurrence event information and for generating time information including an absolute elapsed time from the start of measurement; (B) a buffer for tentatively storing successive event information and time information; a data amount decision unit for deciding a data amount (C1) initially to be in a first stage, (C2) to be in a second stage when the buffer use rate exceeds a first ascending time threshold, and (C3) in the case of the second stage, to have returned to the first stage when the use rate falls below a first descending time threshold smaller than the first ascending time threshold; and a data transfer unit (D1) in the case of the first stage, for transferring the event information and the time information from the buffer to the subsequent stage intact, and (D2) in the case of the second stage, for transferring the event information from the buffer and coarse time information, having degraded accuracy of the time information, successively to the subsequent stage. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种能够在将待观察的测量数据传送到后续阶段时能够有效地执行数据传输的装置等，使得即使测量数据超过传送带，也可以防止测量信息的致命丢失 。 该装置包括：（A）数据接收单元，用于连续接收发生事件信息，并用于产生包括从开始测量开始的绝对经过时间的时间信息; （B）暂时存储连续事件信息和时间信息的缓冲器; 数据量判定单元，用于当缓冲器使用率超过第一上升时间阈值时，决定最初处于第一级的数据量（C1），（C2）为第二级，以及（C3）在 第二阶段，当使用率低于小于第一上升时间阈值的第一下降时间阈值时已经返回到第一阶段; 以及在第一阶段的情况下的数据传送单元（D1），用于将事件信息和时间信息从缓冲器传送到后续阶段，并且（D2）在第二阶段的情况下用于传送事件 来自缓冲器的信息和粗略时间信息，具有降低的时间信息的精度，连续到后续阶段。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009020833A

公开(公告)日：2009-01-29

申请号：JP2007184806

申请日：2007-07-13

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： HARADA NOBUYUKI ,  NAKADA TAKEO

IPC: G06F3/06 ,  G06F12/00 ,  G06F12/08 ,  G06F12/16

CPC classification number: G06F12/0804 ,  Y02D10/13

Abstract: PROBLEM TO BE SOLVED: To efficiently write back data into a main memory from a cache memory. SOLUTION: In a storage device, regarding valid data where logical values showing whether or not each sector is valid are arranged, exclusive OR of each bit of the valid data and other bits adjacent thereto are calculated; a bit stream where the exclusive OR are arranged is bit-masked by eliminating a head bit from bits where the logical values within a set detection range are true; the bit position of the bit where the logical value is true in the bit stream is detected; and every time the bit position is detected, processing for setting a bit position closer to an end side than the bit position as the detection range is repeated until the bit position is not detected; on the basis of the successively detected bit positions, the address of the main memory corresponding to the area is calculated for each area where invalid sectors are continuous; and a read command is issued to the calculated address, and then a cache segment is written back. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：有效地将数据从高速缓冲存储器写回到主存储器中。 解决方案：在存储装置中，对于表示每个扇区是否有效的逻辑值的有效数据进行排列，计算有效数据和与其相邻的其他位的每个位的异或; 排列异或的比特流通过从设置的检测范围内的逻辑值为真的比特中消除头位来进行位掩码; 检测位流中逻辑值为真的位的位位置; 并且每次检测到位位置时，重复将比位位置更靠近端位置的处理作为检测范围进行处理，直到未检测到位位置; 根据连续检测到的比特位置，针对无效扇区连续的每个区域计算与该区域对应的主存储器的地址; 并且向所计算的地址发出读取命令，然后写回高速缓存段。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2003218872A

公开(公告)日：2003-07-31

申请号：JP2002001328

申请日：2002-01-08

Applicant: IBM

Inventor： TAKAHASHI NOBUAKI ,  NAKADA TAKEO ,  OBA NOBUYUKI

IPC: H04L12/28 ,  H04L1/00 ,  H04L1/24 ,  H04L29/14

Abstract: PROBLEM TO BE SOLVED: To enable a long time observation on a signal traffic on a bus in a measurement object system, and enable real time observation in response to operation of the measurement object system. SOLUTION: The apparatus comprises a bus probe device 10 for extracting bus events occurring on the bus based on the digital bus signals on the bus of the measurement object system, a traffic measuring device 20 for counting the number of times of occurrences of the bus events based on the occurrences information on the extracted bus events, and a console unit 30 for processing by acquiring counted values of the measuring device 20. COPYRIGHT: (C)2003,JPO