公开(公告)号：JP2009223572A

公开(公告)日：2009-10-01

申请号：JP2008066695

申请日：2008-03-14

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： OBARA MORIMIKI ,  KOMATSU HIDEAKI

IPC: G06F9/48

CPC classification number: G06F9/541

Abstract: PROBLEM TO BE SOLVED: To convert an existing application program into a batch processing program for collectively processing a plurality of job requests.
SOLUTION: The converter includes: a code identification part for identifying a portion including an access request code for issuing a server processing request to request processing to another server and a portion including a processing code for executing any processing other than the server processing request in an application program; an integration part for converting the access request code in the application program into a collective access request code for collectively issuing a plurality of server processing requests corresponding to a plurality of job requests; a multiplexing part for converting the processing code in the application program into a multiplexed code for executing multiple processing corresponding to the plurality of job requests; and an output part for outputting, as the batch processing program, the application programs that the integration part and the multiplexing part have processed.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：将现有的应用程序转换为批处理程序，以集体处理多个作业请求。 解决方案：转换器包括：代码识别部分，用于识别包括用于发出服务器处理请求的请求代码以用于请求对另一个服务器的处理的部分，以及包括用于执行服务器处理以外的任何处理的处理代码的部分 申请程序中的请求; 用于将应用程序中的访问请求代码转换为用于集体发布与多个作业请求相对应的多个服务器处理请求的集体访问请求代码的集成部分; 用于将应用程序中的处理代码转换为用于执行与多个作业请求相对应的多个处理的多路复用代码的复用部分; 以及输出部，其作为批量处理程序输出积分部和多路复用部已经处理的应用程序。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2008142137A

公开(公告)日：2008-06-26

申请号：JP2006330025

申请日：2006-12-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： OBARA MORIMIKI ,  INOUE HIROSHI ,  KOMATSU HIDEAKI

IPC: A61B6/03 ,  A61B5/055 ,  A61B6/00 ,  G06T7/00

Abstract: PROBLEM TO BE SOLVED: To provide a data processing apparatus, a data processing method, and a program for aligning three-dimensional images. SOLUTION: The data processing apparatus 10 is equipped with down sample processing means 44-48 for lowering the resolution of a fixed image 40, first registering means (50, 52) for performing a registration between the fixed image with the resolution lowered by the down sample processing means 44-48 and the moving image with the lowered resolution like the fixed image with the lowered resolution, and second registering means (54, 56) for performing the registration of the fixed image with the lowered resolution and the moving image with the lowered resolution by using a linear transformation parameter output by the first registering means 52 as an initial value and stores pixel data to be used for the calculation of the mutual information volume in a main memory in a manner to be continuously accessed to execute by fetching the pixel data in a local memory. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供数据处理装置，数据处理方法和用于对准三维图像的程序。 解决方案：数据处理装置10配备有用于降低固定图像40的分辨率的下采样处理装置44-48，用于在降低分辨率的固定图像之间执行对准的第一登记装置（50,52） 通过下采样处理装置44-48和具有降低的分辨率的降低的分辨率的运动图像与分辨率降低的固定图像相关联;以及第二登记装置（54,56），用于以降低的分辨率和移动的方式执行固定图像的登记 通过使用由第一登记装置52输出的线性变换参数作为初始值，降低分辨率的图像，并且以将被连续访问的方式存储在主存储器中用于计算互信息量的像素数据以执行 通过在本地存储器中获取像素数据。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2002278526A

公开(公告)日：2002-09-27

申请号：JP2001062571

申请日：2001-03-06

Applicant: IBM

Inventor： KODA TAKENORI ,  FURUICHI SANEHIRO ,  OBARA MORIMIKI ,  KAWASE KATSURA

IPC: G06F3/153 ,  G06F3/14 ,  G09G3/20 ,  G09G5/00

Abstract: PROBLEM TO BE SOLVED: To drive a large-sized high definition panel merely by adding the change of an extremely small scale to an existing system. SOLUTION: An image display system is provided with a transmitter (PC) 10 for transmitting image data, based on the plotting instruction from an OS or an application and a reception side monitor 40 for displaying the image data received via a monitor cable 39 on a high-definition panel 41. The transmitter 10 is provided with a plot instruction analyzer 20 for detecting an area, where a change is generated on an image by the plotting instruction and calculating the transmission area to be transmitted, on the basis of the detected area and a graphics card 12 for transmitting a packet including the calculated transmission area, which includes the control information of the transmission area in the packet by the form of header data and transmitting it. The reception side monitor 40 is provided with a packet receiver 50, provided with a frame memory for analyzing the header data from the transmitted packet and developing the image data, on the basis of the header data.

公开(公告)号：JP2011008315A

公开(公告)日：2011-01-13

申请号：JP2009148309

申请日：2009-06-23

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： OBARA MORIMIKI

IPC: G06F12/12 ,  G06F12/08

CPC classification number: G06F12/126

Abstract: PROBLEM TO BE SOLVED: To improve performance of an application server by efficiently operating a cache in cooperation with an application.SOLUTION: A method for controlling a cache, includes the steps of: assigning a value corresponding to a transaction to a memory object that is created while an application is processing the transaction; adding the assigned value as a transaction flag value to a flag area of a cache array in accordance with the storage of the memory object in the cache; registering the corresponding transaction flag value as a victim candidate at the completion of the transaction; and during eviction in the cache, preferentially evicting a cache line having the transaction flag value registered as the victim candidate.

Abstract translation: 要解决的问题：通过与应用程序协作高效地操作高速缓存来提高应用服务器的性能。解决方案：一种用于控制高速缓存的方法，包括以下步骤：将与事务相对应的值分配给存储器对象 在应用程序处理事务时创建; 根据存储对象在高速缓存中的存储，将分配的值作为事务标志值添加到高速缓存阵列的标志区域; 在交易完成时将相应的交易标记值注册为受害者候选者; 并且在缓存中的驱逐期间，优先地驱逐具有注册为受害者候选者的交易标志值的高速缓存行。

公开(公告)号：JPH03217963A

公开(公告)日：1991-09-25

申请号：JP466890

申请日：1990-01-16

Applicant: IBM

Inventor： SHIMIZU SHIGENORI ,  OBARA MORIMIKI

IPC: G06F15/16 ,  G06F12/08 ,  G06F12/12 ,  G06F15/177

Abstract: PURPOSE: To improve the performance of a system by detecting a working set and eliminating an unrequired storage block. CONSTITUTION: Working set memories WSM1 -WSMn detect a limited memory space (the limited number of the storage blocks), that is the working set, and register the storage blocks belonging to it. Then, for memory access on a processor and a bus, whether or not the address is present in the registered working set is checked. Also, since the working set is changed in a long time, the storage block not used any more is eliminated from the working set memories WSM1 - WSMn .

公开(公告)号：JP2010128895A

公开(公告)日：2010-06-10

申请号：JP2008304369

申请日：2008-11-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NAKAIKE TAKUYA ,  OBARA MORIMIKI ,  INOUE HIROSHI

IPC: G06F9/52 ,  G06F9/50

Abstract: PROBLEM TO BE SOLVED: To provide a thread execution control method and system for executing a critical section in a complex core, in a heterogeneous multicore processor. SOLUTION: The thread execution control method that uses heterogeneous multicore processor loaded with a plurality of simple cores 30-n and at least one complex core includes: a step in which, when one thread obtains locking of a critical section among the threads currently being executed by the plurality of simple cores 30-n, or at least one complex core 50; the other threads 60 encountering a locking conflict are transferred to the complex core 50 according to the encounter of the other threads 60 with the locking conflict; and a step in which the complex core 50 performs critical section execution of the other threads 60, after the other threads 60 transferred to the complex core 50, obtain locking. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供用于在异构多核处理器中执行复杂核心中的关键部分的线程执行控制方法和系统。 解决方案：使用装载有多个简单核心30-n和至少一个复杂核心的异构多核处理器的线程执行控制方法包括：当一个线程获得线程中的关键部分的锁定时， 目前由多个简单芯30-n或至少一个复合芯50执行; 根据遇到具有锁定冲突的其他线程60的碰撞，遇到锁定冲突的其他线程60被传送到复杂核心50; 并且在另一个螺纹60转移到复合芯50之后，复杂芯部50执行其它螺纹60的临界部分执行的步骤获得锁定。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2007048052A

公开(公告)日：2007-02-22

申请号：JP2005232085

申请日：2005-08-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： OBARA MORIMIKI ,  HAYATA YASUHIKO ,  INOUE HIROSHI ,  MORIYAMA TAKAO ,  KOMATSU HIDEAKI

IPC: G06F9/45

CPC classification number: G06F8/45

Abstract: PROBLEM TO BE SOLVED: To run a program efficiently in a new processor for parallel processing, such as a multi-core processor. SOLUTION: A compiler is provided, which optimizes parallel processing. The compiler records the number of execution cores being the number of processor cores for executing a target program. First, the compiler detects dominant paths being candidates for execution paths to be continuously executed by a single processor core in the target program. Next, the compiler selects the number of dominant paths which is not more than the number of execution cores to thereby generate a cluster of tasks to be parallelly or continuously executed by a multi-core processor. Then, the compiler calculates an execution time when the number of processor cores, equal to one or more natural numbers executes the generated cluster about each of the one or more natural numbers which are not greater than the number of the execution cores for each generated cluster. Then, the number of processor cores to be allocated to execute each cluster is selected on the basis of the calculated execution time. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为了并行处理的新处理器，例如多核处理器，有效地运行程序。 解决方案：提供了一个优化并行处理的编译器。 编译器将执行核心数作为执行目标程序的处理器核心数量。 首先，编译器检测主路径是目标程序中的单个处理器核心连续执行的执行路径的候选。 接下来，编译器选择不大于执行核心数量的主要路径的数量，从而生成要由多核处理器并行或连续执行的任务簇。 然后，编译器计算当等于一个或多个自然数的处理器核心的数量对于每个生成的集群执行生成的集群时，关于每个生成的集群的执行核心数不大于一个或多个自然数的每一个 。 然后，根据计算出的执行时间来选择要分配用于执行每个集群的处理器核心的数量。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2005157955A

公开(公告)日：2005-06-16

申请号：JP2003398823

申请日：2003-11-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： INOUE HIROSHI ,  MORIYAMA TAKAO ,  NEGISHI YASUSHI ,  OBARA MORIMIKI

IPC: G06F9/46 ,  G06F9/48 ,  G06F15/173

CPC classification number: G06F9/4887

Abstract: PROBLEM TO BE SOLVED: To provide a system and a method for increasing the throughput of a system by guaranteeing the deadline of a real-time process on a CPU that uses an SMT, while implementing as many other processes as possible concurrently, and to provide a recording medium on which a program providing the functions thereof is recorded.
SOLUTION: The system includes a measuring part 61 for measuring the computational complexity for a process obtained through a calculation process implemented by a processor 41 serving as a calculation resource; an extra time determining part 62 that causes an interrupt in the calculation process by the processor 41 to obtain the computational complexity obtained up to the time of the interrupt from the measuring part 61 and give the obtained amount of calculations to the processor 41 to calculate extra time and determine whether or not there is extra time; and a process interrupting part 63 that causes the processor 41 to interrupt the calculations of the other processes if the extra time determining part 62 determines that there is no extra time.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供一种系统和方法，通过保证使用SMT的CPU上的实时过程的最后期限来提高系统的吞吐量，同时尽可能多地执行其他过程， 并提供记录有提供其功能的程序的记录介质。 解决方案：该系统包括测量部件61，用于测量由作为计算资源的处理器41实现的计算处理获得的处理的计算复杂度; 额外的时间确定部分62，由处理器41在计算过程中引起中断，以从测量部分61获得直至中断时获得的计算复杂度，并将获得的计算量给予处理器41以计算额外的 时间并确定是否有额外的时间; 以及过程中断部分63，如果额外时间确定部分62确定没有额外的时间，则使得处理器41中断其他进程的计算。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2002259112A

公开(公告)日：2002-09-13

申请号：JP2001039150

申请日：2001-02-15

Applicant: IBM

Inventor： KODA TAKENORI ,  OBARA MORIMIKI ,  NAGAO KATASHI

IPC: G06F17/21 ,  G06F3/14 ,  G06F17/30 ,  G06F40/00 ,  G09G5/00

Abstract: PROBLEM TO BE SOLVED: To provide a display method for enabling a user to understand the contents of a required part in a document and its summary while displaying the whole space without adding specific information to a digital document and destructing document structure such as the order of items. SOLUTION: A digital document reading system is provided with a layout engine 30 for determining the layout of a digital document based on history information concerned with the past display format of the digital document, a summary engine 40 for summarizing sentences in the digital document on the basis of the history information of the digital document, a view generation part 20 for generating information concerned with the display format of the digital document by arranging the summary obtained by the engine 40 in accordance with the determined layout, and a user interface part 10 for displaying the digital document on a display device based on the information concerned with the generated display format.

公开(公告)号：JP2001111651A

公开(公告)日：2001-04-20

申请号：JP28726899

申请日：1999-10-07

Applicant: IBM

Inventor： OBARA MORIMIKI ,  FURUICHI SANEHIRO

IPC: G06F3/153 ,  G06F3/14 ,  G09G5/00 ,  G09G5/36 ,  H04L29/10

Abstract: PROBLEM TO BE SOLVED: To efficiently transmit image data from a computer to a display device. SOLUTION: A scheduler 344 discriminates whether or not increase in a data quantity caused by revision in an image drawing instruction can be cancelled through merging and changes the image drawing instruction when the increase can be cancelled. A communication controller 40 generates a transmission packet including the merged image drawing instruction by a prescribed data amount or over and transmits the packet to the display device.