公开(公告)号：DE1267001B

公开(公告)日：1968-04-25

申请号：DEJ0023799

申请日：1963-05-30

Applicant: IBM

Inventor： KERSEY JAMES R ,  OETERS HAROLD RICHARD ,  TOMASULO ROBERT M ,  JUN FREDERICK M TRAPNELL

IPC: G06F13/22 ,  H04L5/22 ,  H04L7/02 ,  H04L7/033

Abstract: 1,029,940. Data transmission systems. INTERNATIONAL BUSINESS MACHINES CORPORATION. May 30, 1963 [May 31, 1962], No. 21584/63. Heading H4P. In an apparatus in which each received signal bit is sampled during a period short compared with the bit length, transition from one bit to another causes a cyclic timer to reset to zero. The timer, which provides the sampling instant and has a cycle time approximately equal to one bit-duration, is brought into synchronism with the received data each time there is a transition in the data. The basic embodiment, Fig. 1, is shown as a link between a line 1 and a processing unit at 2. Data may pass in either direction. When signals are to be received from the line 1 Receive terminal 11 is energized. AND gate 4 therefore gives an output which enables gate 5a or 5b, dependent on the state of the bit just received. A cyclic counter 10, having variable capacity, normally counts to ten during each bit. At count 6 gate 5a or 5b pulses to trigger binary store which passes a binary signal to the processor. If no data transition has been detected by the time count ten has been reached, counter 10 resets to one via OR gate 21 and AND gate 31. When a transition is detected by the arrangement of delay 24 and EXCL. OR gate 25 counter 10 is reset to one whatever the state of the counter. Thus, although the counter may not be in precise synchronism with the received data it is brought to synchronism at each data transition. During a stop bit which is 40% longer than an ordinary bit the counter cycles once and then counts to four before resetting to one. The processor passes bits to line 1 by way of units 26, 27a, 27b and 28- similar to corresponding units in the reverse direction. However, when an extended stop signal is to be sent terminal 29 is energized, inhibiting the resetting of counter 10 via gate 22. Hence the counter counts to fourteen before resetting so that the stop bit has the correct length. The invention is applied to system for interchange of data among a number of lines. The system is described in detail, and comprises a main frame which scans 15 high-speed lines connected to telegraph transmitter receivers. By means of a multiplexing unit each highspeed line may be served by up to 31 low-speed lines. Control words are allotted to each lowspeed line both in the multiplexer and in the main frame. When the control words coincide during scanning, data is transferred.

公开(公告)号：DE1187264B

公开(公告)日：1965-02-18

申请号：DEJ0024554

申请日：1963-10-12

Applicant: IBM

Inventor： OETERS HAROLD RICHARD ,  HEASSLER REID ASHBY

IPC: G06F13/22 ,  H04L5/22 ,  H04L12/54

Abstract: 1,029,939. Telegraphy. INTERNATIONAL BUSINESS MACHINES CORPORATION. Sept. 30, 1963 [Oct. 15, 1962], No. 38359/63. Heading H4P. In a telegraph exchange a control word is associated with each line for holding data bits and control information. The lines, and hence the stored control words, are scanned sequentially. As described, the scan rate is so fast that an operation on the control word (e.g. removal of one bit forming a character and replacing it with the next bit) takes longer than the relevant control word is available, and the new bit is thus added to the wrong control word. Each control word comprises a number of " correct " and a number of " wrong " bit places, and the invention provides an apparatus wherein a bit entered in the wrong word (i.e. in a " wrong " bit place) is gradually transferred to the " correct " place in the right word. The transference of such a bit from one word to the next takes place direct, whereas the remaining part of the word is passed through the logic section of the exchange and read in to the store in the time-position assigned to that word. In Fig. 1, thirty outgoing lines LA, LB, LC feed remote printers and are scanned in the order A1, A2, A3; B4, B5, B6; C7 &c., but bits are sent only on the first line in each group, i.e. on A1, B4, C7 &c. Whenever a bit is sent to line a new bit is requested from source 1. By the time the new bit arrives on source output 2 the line being scanned will be two ahead of the one for which the new bit was requested. This new bit will therefore be fed in to the wrong control word. Each of the three units MCA comprises a circulating delay line store, this store containing nine ten-bit control words and one bit of the tenth word, the remaining bits of the tenth word being held in a logic unit; the ten words circulate through the store and logic. Whenever bit positions 6, 8 or 10 are read from the store the bits by-pass the logic, which introduces an 8-bit delay, and are read into the store direct. Thus, bit 8 in one word is written into bit-place 10, and on the next circulation passes to bitposition 2. Bit-positions 6, 8, 10 are " wrong " bit-positions. The timing of the arrangement is such that new bits read in to the wrong control word eventually arrive at the right word in position 2. Transference to the right word takes place before the associated line is next required to transmit.