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    2.
    发明专利
    未知

    公开(公告)号：DE1524172A1

    公开(公告)日：1970-03-26

    申请号：DE1524172

    申请日：1966-10-17

    Applicant: IBM

    Inventor： FREDERICK HEILWEIL MELVIN ,  ADRIAN MALEY GERALD ,  RAY MUHLENBRUCH GILBERT ,  OGDEN STEWART

    IPC: G09G1/10 ,  G06F1/02

    Abstract: 1,153,563. Controlling cathode-ray tube displays. INTERNATIONAL BUSINESS MACHINE CORP. 26 Sept., 1966 [18 Oct., 1965], No. 42814/66. Heading G4A. [Also in Division H4] In an arrangement for tracing Alpha-Numeric characters &c. on the screen of a cathode-ray tube means are provided for determining the difference between the co-ordinates of the existing and the next desired position of the electron-beam spot such difference, in respect of each X and Y co-ordinate, being divided into a number of equal portions which are then added in sequence and utilized to produce beam deflection signals. This allows linear deflections to be produced without deflection correction circuits when relatively long traces are involved, especially where the X and Y components are not equal or where one is not zero. In operation, the X and Y co-ordinates are supplied in binary code signals form by a computer operating either in the absolute mode-i.e. the signals represent the absolute end point address of the new trace- or in the relative mode-i.e. the signals represent the quantities to be added to the existing X-Y co-ordinates to give the new end point address. The computer signals appear sequentially at input 11 (Fig. 1) and each signal-i.e. the X and the Y signal, is processed as follows. In accordance with a sequence of timing pulses from counter 42 the X signals are supplied via register 12, shifter 13 (in non-shift position) and gate 14 to adder 15 in which, in the absolute mode, they are algebraically combined with the existing X position signals from register 16 and the difference is inserted in buffer 20 and then inserted in register 44. The Y signals are treated similarly and the difference inserted in buffer 52 and then inserted in register 12. During the operation of adder 15 a cycle control circuit 72 "examines" the two high order bits (N and N-1) therein for both the X and the Y signals and so operates that during the occurence of timing pulse TP7 in the case of the X signals and TP9 in the case of the Y signals shifter 13 effects a shift (e.g. two positions to the right to effect division by four if the N bit of the X or Y difference was 1, this signifying a Vector length of about half screen magnitude) and so controls the counter 42 that it repeats the cycle TP7- TP11 a number of times dependent on the order of division effected by shifter 13. The output of the latter at timing pulses TP7 in respect of the X signals and TP9 in respect of the Y signals is then added in 15 to the count in the position registers 16 and 48 respectively and at timing pulses TP8 and TP10 inserted in buffers 20 and 52 respectively. At timing pulse TP11 the contents of the buffers is transferred to the respective position registers 16, 48 and applied via respective digital-to-analog converting circuits to the X and Y deflection circuits of the display tube. Thus, for each set of X and Y co-ordinate signals from the computer the beam of the display tube is deflected, in each co-ordinate direction, in the same number of incremental steps such number, when the two co-ordinates are of unequal length, being determined by the larger of the two. When the computer signals are in the relative mode the absence of absolute mode pulses TP ABS from the computer output prevents, via AND gates 17 and 49, the application of the contents of position registers 16, 48 to the adder 15 during timing pulses TP1 and TP4 since the difference being now available it is not necessary to determine it in adder 13.

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