公开(公告)号：DE3783796D1

公开(公告)日：1993-03-11

申请号：DE3783796

申请日：1987-02-05

Applicant: IBM

Inventor： HATTORI ETSUO ,  IWAMI TOMOYUKI ,  MIYAZAKI YOSHIHIRO ,  OHBUCHI RYUTAROH

IPC: G06F3/153 ,  G06F3/14 ,  G06T1/00 ,  G06T1/20 ,  G06T11/00 ,  G09G5/393 ,  G09G1/16

Abstract: A display system has a frame buffer comprising a plurality of memory planes, a display device for visually displaying images written into the frame buffer, a controller for controlling image data operations and extended raster operation circuitry comprising an intraplane operation unit for performing operations, specified by the controller, on image data in each of the memory planes, and a separate interplane operation unit for performing operations, specified by the controller, on image data in at least two memory planes selected by the controller, the extended raster operation circuitry being so connected to the memory planes that the results thereof are written back to the frame buffer. The interplane operation unit consists of a plurality of operation circuits respectively corresponding to the plurality of memory planes, and a plurality of delay means respectively related to the plurality of operation circuits, each of the operation circuits receives, as the inputs, image data in a memory plane selected by the command and its own output delayed a predetermined period of time by the related delay means, and the final operation result only is written into the corresponding memory plane.

公开(公告)号：DE3783796T2

公开(公告)日：1993-08-19

申请号：DE3783796

申请日：1987-02-05

Applicant: IBM

Inventor： HATTORI ETSUO ,  IWAMI TOMOYUKI ,  MIYAZAKI YOSHIHIRO ,  OHBUCHI RYUTAROH

IPC: G06F3/153 ,  G06F3/14 ,  G06T1/00 ,  G06T1/20 ,  G06T11/00 ,  G09G5/393 ,  G09G1/16

Abstract: A display system has a frame buffer comprising a plurality of memory planes, a display device for visually displaying images written into the frame buffer, a controller for controlling image data operations and extended raster operation circuitry comprising an intraplane operation unit for performing operations, specified by the controller, on image data in each of the memory planes, and a separate interplane operation unit for performing operations, specified by the controller, on image data in at least two memory planes selected by the controller, the extended raster operation circuitry being so connected to the memory planes that the results thereof are written back to the frame buffer. The interplane operation unit consists of a plurality of operation circuits respectively corresponding to the plurality of memory planes, and a plurality of delay means respectively related to the plurality of operation circuits, each of the operation circuits receives, as the inputs, image data in a memory plane selected by the command and its own output delayed a predetermined period of time by the related delay means, and the final operation result only is written into the corresponding memory plane.

公开(公告)号：CA1270344A

公开(公告)日：1990-06-12

申请号：CA532019

申请日：1987-03-13

Applicant: IBM

Inventor： HATTORI ETSUO ,  IWAMI TOMOYUKI ,  MIYAZAKI YOSHIHIRO ,  OHBUCHI RYUTAROH

IPC: G06F3/153 ,  G06F3/14 ,  G06T1/00 ,  G06T1/20 ,  G06T11/00 ,  G09G5/393 ,  G09G1/16

Abstract: A display system having a frame buffer comprising a plurality of memory planes includes a display device for visually displaying images written into the frame buffer. A controller controls image data operations, and the system is characterized in that it is provided with an extended raster operation circuitry comprising an intraplane operation unit for performing operations, specified by the controller, on image data in each of the memory planes. An interplane operation unit performs operations, specified by the controller, on image data in at least two memory planes selected by the controller, and operation results of the circuitry are written back to the frame buffer.