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公开(公告)号：EP0694826A3
公开(公告)日：1998-05-13
申请号：EP95305186
申请日：1995-07-25
Applicant: IBM
Inventor： NARITA IZURU , IWAMI TOMOYUKI
CPC classification number: G05F1/577 , H02M3/33561
Abstract: The present invention relates to an information processing apparatus that comprises a plurality of electric circuits and that has power supply lines for the individual electric circuits. It provides a switching regulator that controls the power that is supplied by an external power source to such an information processing apparatus, while inhibiting power waste, and the information processing apparatus and a method for its control.
The information processing apparatus, which is activated by power supplied from an external power source, comprises: a first power supply line for supplying power to a first electric circuitry; a second power supply line for supplying power to a second electric circuitry; a i-th power supply line for supplying power to a i-th electric circuitry (i is an integer of 1 ≦ i ≦ n, and n is an integer equal to 2 or greater); means for monitoring a first voltage of the first power supply line; means for monitoring a second voltage of the second power supply line; means for monitoring a i-th voltage of the i-th power supply line; means for selecting the minimum voltage among the first through the i-th voltages; means for comparing the minimum voltage with a previously given reference voltage; and connecting/disconnecting means for starting or halting the power supply from the external power source in response to the comparison result. As the lowest voltage can be used as a feedback target, the application of a high voltage is not required even if the safety of the system is taken into consideration and power will not be wasted.Abstract translation: 信息处理装置技术领域本发明涉及包括多个电路并且具有用于各个电路的电源线的信息处理装置。 它提供了一种开关调节器，其在抑制电力浪费的同时，将由外部电源提供的功率控制到这种信息处理装置，以及信息处理装置及其控制方法。 由从外部电源供给的电力启动的信息处理装置包括：用于向第一电路供电的第一电源线; 用于向第二电路供电的第二电源线; 用于向第i个电路供电的第i个电源线（i为1的整数，n为等于2或更大的整数）; 用于监视第一电源线的第一电压的装置; 用于监视第二电源线的第二电压的装置; 用于监视第i个电源线的第i个电压的装置; 用于选择第一至第i电压中的最小电压的装置; 用于将最小电压与先前给定的参考电压进行比较的装置; 以及用于响应于比较结果从外部电源启动或停止电源的连接/断开装置。 由于最低电压可以用作反馈目标，因此即使考虑到系统的安全性并且不会浪费电力，也不需要施加高电压。
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公开(公告)号：JPH0847251A
公开(公告)日：1996-02-16
申请号：JP17820494
申请日：1994-07-29
Applicant: IBM
Inventor： NARITA IZURU , IWAMI TOMOYUKI
Abstract: PURPOSE: To provide a switching regulator, an information processor and the control method for controlling power supply from an external power source to the information processor, without dissipating wasteful power with an information processor constituted of plural electric circuit systems and provided with power supply lines for the respective electric circuit systems as an object. CONSTITUTION: This information processor, which is driven by supplied power from the external power source, is provided with a means 51 for selecting a minimum voltage from first - (n)-th power supply lines, the means for comparing the minimum voltage with a reference voltage set beforehand and a connection/interruption means 23 for starting or interrupting the supply of the power from the external power source, corresponding to the result of a comparison. Also, since the lower voltage is used as the object of feedback, the need for applying for a higher voltage in anticipation of the maintenance of a system is eliminated, and the wasteful power does not need to the supplied.
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公开(公告)号：JPS62245375A
公开(公告)日：1987-10-26
申请号：JP8227586
申请日：1986-04-11
Applicant: IBM
Inventor： HATTORI ETSUO , IWAMI TOMOYUKI , MIYAZAKI YOSHIHIRO , OBUCHI RYUTARO
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Patent Agency Ranking
公开(公告)号：CA1236600A
公开(公告)日：1988-05-10
申请号：CA478891
申请日：1985-04-11
Applicant: IBM
Inventor： IWAMI TOMOYUKI
Abstract: A raster scan display system is provided for composition of plural frame color images. First and second frame buffers, which store first and second frame color images respectively, are accessed in synchronization with a CRT. Then the first and the second frame streams of color pel data are generated from the first and the second frame buffers respectively. Subsequently the first stream of color pel data is compared with a predetermined color, and at the time when the comparison indicates that the colors are not the same, the first stream of color pel data is sent to the CRT. When the comparison indicates that the colors are the same, however, the second stream of color pel data is sent instead. Consequently, the first frame color image except of the part of the predetermined color is superimposed on the second frame color image. It is as if the part of the predetermined color in the first frame color image becomes transparent.
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公开(公告)号：DE3783796T2
公开(公告)日：1993-08-19
申请号：DE3783796
申请日：1987-02-05
Applicant: IBM
Inventor： HATTORI ETSUO , IWAMI TOMOYUKI , MIYAZAKI YOSHIHIRO , OHBUCHI RYUTAROH
Abstract: A display system has a frame buffer comprising a plurality of memory planes, a display device for visually displaying images written into the frame buffer, a controller for controlling image data operations and extended raster operation circuitry comprising an intraplane operation unit for performing operations, specified by the controller, on image data in each of the memory planes, and a separate interplane operation unit for performing operations, specified by the controller, on image data in at least two memory planes selected by the controller, the extended raster operation circuitry being so connected to the memory planes that the results thereof are written back to the frame buffer. The interplane operation unit consists of a plurality of operation circuits respectively corresponding to the plurality of memory planes, and a plurality of delay means respectively related to the plurality of operation circuits, each of the operation circuits receives, as the inputs, image data in a memory plane selected by the command and its own output delayed a predetermined period of time by the related delay means, and the final operation result only is written into the corresponding memory plane.
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公开(公告)号：CA1270344A
公开(公告)日：1990-06-12
申请号：CA532019
申请日：1987-03-13
Applicant: IBM
Inventor： HATTORI ETSUO , IWAMI TOMOYUKI , MIYAZAKI YOSHIHIRO , OHBUCHI RYUTAROH
Abstract: A display system having a frame buffer comprising a plurality of memory planes includes a display device for visually displaying images written into the frame buffer. A controller controls image data operations, and the system is characterized in that it is provided with an extended raster operation circuitry comprising an intraplane operation unit for performing operations, specified by the controller, on image data in each of the memory planes. An interplane operation unit performs operations, specified by the controller, on image data in at least two memory planes selected by the controller, and operation results of the circuitry are written back to the frame buffer.
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公开(公告)号：DE3783796D1
公开(公告)日：1993-03-11
申请号：DE3783796
申请日：1987-02-05
Applicant: IBM
Inventor： HATTORI ETSUO , IWAMI TOMOYUKI , MIYAZAKI YOSHIHIRO , OHBUCHI RYUTAROH
Abstract: A display system has a frame buffer comprising a plurality of memory planes, a display device for visually displaying images written into the frame buffer, a controller for controlling image data operations and extended raster operation circuitry comprising an intraplane operation unit for performing operations, specified by the controller, on image data in each of the memory planes, and a separate interplane operation unit for performing operations, specified by the controller, on image data in at least two memory planes selected by the controller, the extended raster operation circuitry being so connected to the memory planes that the results thereof are written back to the frame buffer. The interplane operation unit consists of a plurality of operation circuits respectively corresponding to the plurality of memory planes, and a plurality of delay means respectively related to the plurality of operation circuits, each of the operation circuits receives, as the inputs, image data in a memory plane selected by the command and its own output delayed a predetermined period of time by the related delay means, and the final operation result only is written into the corresponding memory plane.
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公开(公告)号：BR8501646A
公开(公告)日：1985-12-03
申请号：BR8501646
申请日：1985-04-09
Applicant: IBM
Inventor： IWAMI TOMOYUKI
Abstract: Digital display data is stored in first and second memories which are accessed together to provide respective streams of picture element data groups for display on a raster scan display device. A comparator compares each data group from a selected one of the streams with a data group representing a particular color. The comparator output is applied as a control input to a multiplexer which also receives the data streams. When no equality is detected, the multiplexer passes the data groups in the compared stream through to the display device. Whenever equality is detected the multiplexer passes the corresponding data group in the non-compared stream through to the display device. The result is that the displayed image corresponding to the compared stream is made transparent at areas corresponding to the compared color, and there areas are filled in with an image corresponding to data from the non-compared stream of data.
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