公开(公告)号：JPH11186910A

公开(公告)日：1999-07-09

申请号：JP32456997

申请日：1997-11-26

Applicant: IBM

Inventor： OKADA ITOKU ,  TANAKA KEISUKE ,  USHIO TERUHIKO

IPC: G11B20/14 ,  H03M7/14 ,  H03M7/46

Abstract: PROBLEM TO BE SOLVED: To reduce the consumption of memory resources through a single processing route by identifying first and second channel bits, removing a pattern not present on a first PLL rule from the patterns of first channel bit display, generating an output bit and removing the pattern not present in a second PLL rule from the patterns of second channel bit display. SOLUTION: The 8/16 modulated or EFM modulated channel bits of 16 bits or 14 bits are inputted through an input line to the data input of a buffer register 500, and the data of the channel bits are stored for 8 bits in a higher order and for 8 or 6 bits in a lower order by loading control from an arithmetic control circuit 550. The data of the upper 8 bits of the buffer register 500 are sent to a demultiplexer 501, and for medium information from an arithmetic circuit 550, the data of the lower 8 bits are sent to an 8/16 bit operation I circuit 511 at the time of a DVD and the lower 6 bits are sent to a bit operation III circuit 530 at a CD time.