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Patent Agency Ranking
公开(公告)号：JP2000113606A
公开(公告)日：2000-04-21
申请号：JP28223398
申请日：1998-10-05
Applicant: IBM
Inventor： USHIO TERUHIKO , KANAI TOSHIO
IPC: G11B20/18
Abstract: PROBLEM TO BE SOLVED: To revise a bit shift error irrespective of ECC by a method wherein a read signal from a medium is converted into a bit string, and a gray bit having possibilities in an error in the bit string to generate gray bit information, and an error bit is corrected from the information, and the corrected bit string is decoded. SOLUTION: A read channel 11 converts a read signal from a medium 10 into a read data 13 comprising a bit string, and a gray bit 14 having possibilities in an error in a bit string is detected by a gray bit detection circuit 12, and is fed to a decoder 16 via a mark detector 15. The decoder 16 inspects data from the gray bit 14 in a RLL(run length limited) error correction circuit 17, and corrects a discovered data error during transfer to a conversion table 18, and the corrected data are decoded by the conversion table 18. At this time, an error correction is made by an error correction circuit 19 using a conversion table.
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公开(公告)号：JPH11186910A
公开(公告)日：1999-07-09
申请号：JP32456997
申请日：1997-11-26
Applicant: IBM
Inventor： OKADA ITOKU , TANAKA KEISUKE , USHIO TERUHIKO
Abstract: PROBLEM TO BE SOLVED: To reduce the consumption of memory resources through a single processing route by identifying first and second channel bits, removing a pattern not present on a first PLL rule from the patterns of first channel bit display, generating an output bit and removing the pattern not present in a second PLL rule from the patterns of second channel bit display. SOLUTION: The 8/16 modulated or EFM modulated channel bits of 16 bits or 14 bits are inputted through an input line to the data input of a buffer register 500, and the data of the channel bits are stored for 8 bits in a higher order and for 8 or 6 bits in a lower order by loading control from an arithmetic control circuit 550. The data of the upper 8 bits of the buffer register 500 are sent to a demultiplexer 501, and for medium information from an arithmetic circuit 550, the data of the lower 8 bits are sent to an 8/16 bit operation I circuit 511 at the time of a DVD and the lower 6 bits are sent to a bit operation III circuit 530 at a CD time.
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公开(公告)号：JP2000112776A
公开(公告)日：2000-04-21
申请号：JP27191298
申请日：1998-09-25
Applicant: IBM
Inventor： USHIO TERUHIKO , YAMADA MITSUHARU , KANAI TOSHIO , KUNIEDA EIJI
Abstract: PROBLEM TO BE SOLVED: To provide an error correction system which reduces a time needed for error correction processing in a form of product code and can improve use efficiency of a buffer storage device by efficiently performing data transfer. SOLUTION: This error correction system includes a formatter 20 for generating an ECC block which includes data arrayed in a matrix and at least a line error correction code for each line. A syndrome generator 38 is included between the formatter 20 and a first buffer storage device 22. The syndrome generator 38 generates a syndrome on the basis of each ECC block line from the formatter 20. An ECC block line and a related syndrome are stored in the first buffer storage device 22. Only the syndrome in the first buffer storage device 22 is transferred to a second buffer storage device 24 and an error correction code decoder 26. The first buffer storage device 22 stores data by a bank interleave system and the syndrome is stored at an empty position of the first buffer storage device 22.
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公开(公告)号：JP2001216741A
公开(公告)日：2001-08-10
申请号：JP2000022327
申请日：2000-01-31
Applicant: IBM
Inventor： USHIO TERUHIKO
Abstract: PROBLEM TO BE SOLVED: To reduce the size of a table where conversion codes corresponding to an input code is stored and to improve the converting speed of a code. SOLUTION: A code modulator 10 is provided with a conversion table 14 storing the conversion code obtained by omitting an overlapped code from among plural conversion codes corresponding to the input code, a preprocessing table 18 storing the corresponding relation (overlapped information, hereafter) between the omitted conversion code and a conversion code in the table 14 overlapped with this omitted conversion code, code designating means 26 and 28 for designating a conversion code to be used from among the plural conversion codes and a code conversion means 12 for reading the conversion code corresponding to the input code from the table 14 based on designation by the means 26 and 28 and the overlapped information in the table 18.
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公开(公告)号：JP2000090439A
公开(公告)日：2000-03-31
申请号：JP25393698
申请日：1998-09-08
Applicant: IBM
Inventor： KANAI TOSHIO , USHIO TERUHIKO
IPC: G11B20/10 , G11B7/00 , G11B7/005 , G11B19/28 , G11B20/14 , G11B27/30 , G11B27/34 , G11B27/36 , G11B19/06
Abstract: PROBLEM TO BE SOLVED: To obtain an exact frequency by saving a measured mark length, measuring the mark continuous with this mark, determining the sum of the saved mark length and the freshly measured mark length and detecting the sum of he lengths of the longest mark and the mark continuous with this mark as the max. mark length. SOLUTION: The total value of the mark lengths is saved from the point of the time the max. value of the sum of the lengths of the continuous marks is measured by a total register 12 for which an arbitrary memory element capable of reading-out and writing is used. A measured value register 14 is capable of using the arbitrary memory element capable of saving at least the previously measured mark lengths and reading out and writing these mark lengths. An arithmetic and logic unit 22 determines the sum of the previously measured mark length and the mark length measured this time, adds the measured value of this time to the tote value and subtracts the max. value from the total value, for which an arbitrary arithmetic circuit capable of making at least addition, subtraction and division is used.
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