中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

6 records (took 0.028 seconds)

    Dynamic power supply test system
    3.
    发明授权
    Dynamic power supply test system 失效
    动态电源测试系统

    公开(公告)号：US3867618A

    公开(公告)日：1975-02-18

    申请号：US37353973

    申请日：1973-06-25

    Applicant: IBM

    Inventor： OLIVER BURTON L ,  SITLER WAYNE R

    IPC: G06F11/00 ,  G01R31/02 ,  G01R31/317 ,  G06F1/28 ,  H02J9/00

    CPC classification number: G01R31/02 ,  G01R31/317

    Abstract: A test system is connected to power supply means in a data processing system to detect and locate faults which occur due to power supply loading conditions. The data processing system has several functional units, each of which is powered by separate power supply means. The test system which is connected to and monitors the output of each of the power supply means includes filtering means for separating high frequency components from low frequency components, positive and negative polarity level detection means for the high frequency components and for the low frequency components and direct current positive and negative threshold detectors. When the system is in the power test mode, the outputs from the level and threshold detectors are gated to voltage status registers which are periodically interrogated by the data processing system to determine if a fault has occurred due to power supply loading conditions.

    Abstract translation: 测试系统连接到数据处理系统中的电源装置，以检测和定位由于电源负载条件而发生的故障。 数据处理系统具有多个功能单元，每个功能单元由单独的电源装置供电。 连接并监视每个电源装置的输出的测试系统包括用于从低频分量分离高频分量的滤波装置，用于高频分量和低频分量的正极性和极性电平检测装置， 直流正负检测器。 当系统处于电源测试模式时，来自电平和阈值检测器的输出被门控到由数据处理系统周期性询问的电压状态寄存器，以确定是否由于电源负载条件而发生故障。

    APPARATUS AND METHOD FOR DIRECT MEMORY TO PERIPHERAL AND PERIPHERAL TO MEMORY DATA TRANSFERS
    5.
    发明专利
    APPARATUS AND METHOD FOR DIRECT MEMORY TO PERIPHERAL AND PERIPHERAL TO MEMORY DATA TRANSFERS 未知

    公开(公告)号：CA1208802A

    公开(公告)日：1986-07-29

    申请号：CA462900

    申请日：1984-09-11

    Applicant: IBM

    Inventor： BUONOMO JOSEPH P ,  LOSINGER RAYMOND E ,  OLIVER BURTON L

    IPC: G06F13/10 ,  G06F9/38 ,  G06F12/06 ,  G06F13/38 ,  G06F15/16 ,  G06F15/177 ,  G06F13/36 ,  G06F9/22

    Abstract: A multi-microprocessor implemented data processing system having a single cycle data transfer capability for its memory mapped peripheral devices is described. A host or controlling microprocessor provides address and control signals for memory accesses. In addition, it also determines that a peripheral operation is desired. When this occurs, a command is sent to the selected peripheral and a memory cycle, fetch or store, for the data transfer is initiated. The address bus is provided with the memory address for the needed data and a special decode that indicates the unique nature of this memory access. Logic circuit means are provided to detect the special decode and to intercept the data bus at the appropriate point in the bus cycle in response thereto. The logic circuit means is adapted to then responsively apply the correct control signals to the peripheral to enable the desired data transfer after the data bus has been intercepted.

Patent Agency Ranking