公开(公告)号：JP2001346205A

公开(公告)日：2001-12-14

申请号：JP2001084465

申请日：2001-03-23

Applicant: IBM

Inventor： ERIC M FOSTER ,  FRANKLIN DENNIS E ,  LAM WAI MAN ,  LOSINGER RAYMOND E ,  NGAI CHUCK H

IPC: G06F11/10 ,  G11B20/10 ,  G11B20/18 ,  H03M13/37 ,  H04L1/00 ,  H04N19/00 ,  H04N19/89 ,  H04N21/43 ,  H04N21/44 ,  H04N21/4425 ,  H04N7/24

Abstract: PROBLEM TO BE SOLVED: To provide enhanced error recovery in the process of storing digitally transmitted audio and video signals. SOLUTION: Data damaged or lost when being sent via an irreversible compression digital transmission link are replaced with data given in relation to storage to and read from a mass storage device and/or deleted. A different procedure is used to conceal an artifact corresponding to error data based on a size of valid data and an error preceding and succeeding to an error in a data stream.

公开(公告)号：CA1182573A

公开(公告)日：1985-02-12

申请号：CA424284

申请日：1983-03-23

Applicant: IBM

Inventor： AGNEW PALMER W ,  BUONOMO JOSEPH P ,  HOUGHTALEN STEVEN R ,  KELLERMAN ANNE S ,  LOSINGER RAYMOND E ,  VALASHINAS JAMES W

IPC: G06F9/455 ,  G06F9/22 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/16

Abstract: METHODS FOR PARTITIONING MAINFRAME INSTRUCTION SETS TO IMPLEMENT MICROPROCESSOR BASED EMULATION THEREOF Methods of applying LSI and microprocessors to the design of microprocessor-based LSI implementation of mainframe processors are described. The mainframe instruction set is partitioned into two or more subsets, each of which can be implemented by a microprocessor having special on-chip microcode or by a standard off-the-shelf microprocessor running programs written for that purpose. Alternatively, one or more of the subsets can be implemented by a single microprocessor. In addition, a subset of the partitioned instruction set can be implemented by emulating software, by off chip vertical or horizontal microcode, or by primitives. But, however partitioning is implemented, the end result thereof is to keep the critical flow paths, associated with the most frequently used instruction subset, as short as possible by constraining them to a single chip.

公开(公告)号：CA1208802A

公开(公告)日：1986-07-29

申请号：CA462900

申请日：1984-09-11

Applicant: IBM

Inventor： BUONOMO JOSEPH P ,  LOSINGER RAYMOND E ,  OLIVER BURTON L

IPC: G06F13/10 ,  G06F9/38 ,  G06F12/06 ,  G06F13/38 ,  G06F15/16 ,  G06F15/177 ,  G06F13/36 ,  G06F9/22

Abstract: A multi-microprocessor implemented data processing system having a single cycle data transfer capability for its memory mapped peripheral devices is described. A host or controlling microprocessor provides address and control signals for memory accesses. In addition, it also determines that a peripheral operation is desired. When this occurs, a command is sent to the selected peripheral and a memory cycle, fetch or store, for the data transfer is initiated. The address bus is provided with the memory address for the needed data and a special decode that indicates the unique nature of this memory access. Logic circuit means are provided to detect the special decode and to intercept the data bus at the appropriate point in the bus cycle in response thereto. The logic circuit means is adapted to then responsively apply the correct control signals to the peripheral to enable the desired data transfer after the data bus has been intercepted.

公开(公告)号：BR8705234A

公开(公告)日：1988-05-24

申请号：BR8705234

申请日：1987-10-02

Applicant: IBM

Inventor： BUONOMO JOSEPH P ,  CALLAHAN ROBERT W ,  HOUGHTALEN STEVEN R ,  KODUKULA SIVARAMA K ,  LOSINGER RAYMOND E ,  SHIMAMOTO BRION N ,  TREDENNICK H L ,  VALASHINAS JAMES W

IPC: G06F9/455 ,  G06F9/318 ,  G06F9/44