公开(公告)号：US3906485A

公开(公告)日：1975-09-16

申请号：US36967573

申请日：1973-06-13

Applicant: IBM

Inventor： HONG SE J ,  OSTAPKO DANIEL L

IPC: H03M7/40 ,  G11B20/14 ,  H04L25/48 ,  H04L25/49 ,  H03K13/24

CPC classification number: H04L25/4906 ,  G11B20/1426

Abstract: The encoding circuits of this invention provide signals for representing binary data in a storage medium or in a transmission system as a waveform that has a small constrained value of accumulated difference between its positive and negative portions. The waveform has minimum and maximum run lengths between transitions between positive and negative values so that it provides both high density and good clocking. Several new codes are described which can be implemented with fewer logic and storage components than prior codes of this general type.

Abstract translation: 本发明的编码电路提供用于在存储介质或传输系统中表示二进制数据的信号，作为其正负部分之间具有小的累积差的约束值的波形。 波形在正值和负值之间的转换之间具有最小和最大运行长度，从而提供高密度和良好的时钟。 描述了可以使用比该通用类型的先前代码更少的逻辑和存储组件来实现的几个新代码。

公开(公告)号：JP2005244978A

公开(公告)日：2005-09-08

申请号：JP2005045001

申请日：2005-02-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GUPTA PUNEET ,  HENG FOOK-LUEN ,  KUNG DAVID S ,  OSTAPKO DANIEL L

IPC: H01L27/118 ,  G06F17/50 ,  H01L21/82 ,  H01L27/02 ,  H01L27/092 ,  H01L29/00 ,  H03K5/13

CPC classification number: H01L27/0207 ,  H01L27/092

Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit (IC) including at least one combined logic circuit.
SOLUTION: The combined logic circuit includes two types of logic block cells for mutually correcting the influence caused by manufacturing parameters which affect cell transistors. The two types of cells can be made as a condensed cell, having FET gates with a contact pitch and a separated cell, having FET gates with a pitch wider than the contact pitch. Variations in the delay of the condensed cell caused by the FET gates being printed, while being out of focus, can be offset by the the variations in the delay of the separated cell.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种包括至少一个组合逻辑电路的集成电路（IC）。 解决方案：组合逻辑电路包括两种类型的逻辑块单元，用于相互校正影响单元晶体管的制造参数所引起的影响。 两种类型的电池可以制成为具有接触间距的FET栅极和分离电池的冷凝单元，具有比接触间距更宽的间距的FET栅极。 由被打印的FET栅极引起的冷凝单元的延迟在偏离聚焦的情况下的变化可以被分离的单元的延迟的变化所抵消。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：FR2331209A1

公开(公告)日：1977-06-03

申请号：FR7629484

申请日：1976-09-22

Applicant: IBM

Inventor： HONG SE J ,  OSTAPKO DANIEL L

IPC: H03K19/177 ,  H03M7/00 ,  H03K13/25 ,  H03K19/08

Abstract: This specification describes a decoder for a programmable logic array (PLA) having opposite ends of input lines of the array connected to outputs of different decoders. Previously two-bit decoders were arranged on opposite sides of the array to generate input variables from two sets of two different input signals each and feed those input variables to four input lines. Here, instead of using two-bit decoders, four one-bit decoders are positioned on each side. The outputs of these one-bit decoders are programmable to change the connections between them and the input lines of the array. The arrangement permits the decoders to perform one-bit, two-bit decoding on signals on the same side of the input lines, to do two-bit decoding on signals on opposite sides of the array and in combination with other sets of decoders to do three and four-bit decoding of input signals.

公开(公告)号：FR2295645A1

公开(公告)日：1976-07-16

申请号：FR7533266

申请日：1975-10-20

Applicant: IBM

Inventor： HONG SE J ,  OSTAPKO DANIEL L

IPC: G06F11/22 ,  G01R31/3185 ,  G06F11/10 ,  H03K19/177 ,  H03K19/00

Abstract: 1475255 Selective signalling INTERNATIONAL BUSINESS MACHINES CORP 1 Oct 1975 [18 Dec 1974] 40080/75 Heading G4H A logic array with testing apparatus comprises a plurality of decoders feeding input lines of a logic-performing matrix, the matrix incorporating a check line intersecting the input lines for storing information on the number of operative logic means located along each of the input lines. In Fig. 1, input bits at 14 are decoded in pairs by decoders 12a, 12b ... 12, each decoder selecting one of a respective 4 row lines of an AND array 10. The array 10 has FETs at selected row-column intersections to provide on each column line the AND of a respective combination of the row lines. The column lines feed an OR array 24 which similarly has FETs at selected row-column intersections and feeds latches via its row lines. The AND array has an extra column line 21 specifying a parity bit for each row line according to the number of FETs which should be present in it, and the OR array has an extra row line 19 specifying a parity bit for each column line. To test the AND array, a command decoder 36 is used to enable the decoders 12a, 12b ... 12 in turn, each decoder, when enabled, being supplied with appropriate inputs to select all its outputs in turn. As each row line of the AND array is thus selected, the column outputs are loaded into a shift register 48 and parity-checked by an EXCL-OR tree 50. The OR array is then tested by decoupling the two arrays using a mask output 40 of the command decoder 36, and inserting a 1 into the shift register 48 and shifting it along thus selecting the column lines of the OR array in turn, the row outputs being parity-checked in each case by an EXCL-OR tree 54. Another output 42 of the command decoder 36 (used e.g. for normal operation) enables all the decoders 12a, 12b ... 12 and resets the shift register 48. EXCL-ORing may be done serially. Extra redundancy lines could be provided in the arrays.

公开(公告)号：CA1040270A

公开(公告)日：1978-10-10

申请号：CA237270

申请日：1975-10-08

Applicant: IBM

Inventor： HONG SE J ,  OSTAPKO DANIEL L

IPC: G06F11/22 ,  G01R31/3185 ,  G06F11/10 ,  H03K19/177 ,  G06F11/00

Abstract: This specification describes arrays for performing logic functions which include circuitry for testing the arrays to see if the arrays will perform the logic functions that they were designed to perform. During testing, a gating signal to each of the decoders is used to couple the interrogatior signals of one of these decoders at a time to the input lines of the array. This allows the interrogation of one input line at a time and the detection of the output signals produced by that interrogation on the output lines of the array. To determine whether the output signals are proper, the array contains one or more additional output lines which contain parity or check bits on the circuit elements arranged along each of the input lines. When an input line is interrogated the output signals including those produced by the parity or check bits are exclusively OR'd to determine if the interrogated input line contains the proper number of circuit elements. This circuitry eliminates the need for storing information as to logic functions performed by any particular array and allows a uniform testing sequence to be used in testing all the arrays.

公开(公告)号：DE2550342A1

公开(公告)日：1976-06-24

申请号：DE2550342

申请日：1975-11-08

Applicant: IBM

Inventor： HONG SE J ,  OSTAPKO DANIEL L

IPC: G06F11/22 ,  G01R31/3185 ,  G06F11/10 ,  H03K19/177 ,  G01R31/28

Abstract: 1475255 Selective signalling INTERNATIONAL BUSINESS MACHINES CORP 1 Oct 1975 [18 Dec 1974] 40080/75 Heading G4H A logic array with testing apparatus comprises a plurality of decoders feeding input lines of a logic-performing matrix, the matrix incorporating a check line intersecting the input lines for storing information on the number of operative logic means located along each of the input lines. In Fig. 1, input bits at 14 are decoded in pairs by decoders 12a, 12b ... 12, each decoder selecting one of a respective 4 row lines of an AND array 10. The array 10 has FETs at selected row-column intersections to provide on each column line the AND of a respective combination of the row lines. The column lines feed an OR array 24 which similarly has FETs at selected row-column intersections and feeds latches via its row lines. The AND array has an extra column line 21 specifying a parity bit for each row line according to the number of FETs which should be present in it, and the OR array has an extra row line 19 specifying a parity bit for each column line. To test the AND array, a command decoder 36 is used to enable the decoders 12a, 12b ... 12 in turn, each decoder, when enabled, being supplied with appropriate inputs to select all its outputs in turn. As each row line of the AND array is thus selected, the column outputs are loaded into a shift register 48 and parity-checked by an EXCL-OR tree 50. The OR array is then tested by decoupling the two arrays using a mask output 40 of the command decoder 36, and inserting a 1 into the shift register 48 and shifting it along thus selecting the column lines of the OR array in turn, the row outputs being parity-checked in each case by an EXCL-OR tree 54. Another output 42 of the command decoder 36 (used e.g. for normal operation) enables all the decoders 12a, 12b ... 12 and resets the shift register 48. EXCL-ORing may be done serially. Extra redundancy lines could be provided in the arrays.