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    Bi-directional differential low power sense amp and memory system
    1.
    发明授权
    Bi-directional differential low power sense amp and memory system 有权
    双向差分低功率检测放大器和存储器系统

    公开(公告)号：US6363023B2

    公开(公告)日：2002-03-26

    申请号：US79295901

    申请日：2001-02-26

    Applicant: IBM

    Inventor： ANDERSEN JOHN E ,  OUELLETTE MICHAEL R

    IPC: G11C7/06 ,  G11C11/419 ,  G11C7/02

    CPC classification number: G11C11/419 ,  G11C7/065

    Abstract: A device and method is provided for reducing power consumption in memory devices. The preferred embodiment reduces power consumption by providing a sense amplifier that reduces power consumption while providing high performance. In the preferred embodiment the sense amplifier comprises a bi-directional sense amp that is configurable for use on low power static random access memory (SRAM) devices. The bi-directional sense amp allows the same sense amp to be used for both read and write operations on the memory cells. The preferred embodiment sense amp facilitates the use of differential data buses, further reducing power consumption while providing high performance. Thus, the preferred embodiment bi-directional differential sense amp reduces the device size and complexity, reducing power consumption while providing high performance memory access.

    Abstract translation: 提供了一种用于降低存储器件中的功耗的装置和方法。 优选实施例通过提供在提供高性能的同时降低功耗的读出放大器来降低功耗。 在优选实施例中，读出放大器包括可配置用于低功率静态随机存取存储器（SRAM）器件的双向读出放大器。 双向读出放大器允许将相同的感测放大器用于存储器单元上的读取和写入操作。 优选实施例的感测放大器有助于使用差分数据总线，进一步降低功耗，同时提供高性能。 因此，优选实施例的双向差分检测放大器降低了器件尺寸和复杂性，降低了功耗，同时提供了高性能的存储器访问。

    LOW VOLTAGE PROGRAMMABLE eFUSE WITH DIFFERENTIAL SENSING SCHEME
    2.
    发明公开
    LOW VOLTAGE PROGRAMMABLE eFUSE WITH DIFFERENTIAL SENSING SCHEME 有权
    可编程低压差分的eFuse读法

    公开(公告)号：EP1800323A4

    公开(公告)日：2008-11-26

    申请号：EP05794850

    申请日：2005-09-01

    Applicant: IBM

    Inventor： OUELLETTE MICHAEL R ,  WISSEL LARRY

    IPC: H01H37/76 ,  G11C17/16 ,  G11C17/18 ,  G11C29/02 ,  G11C29/50

    CPC classification number: G11C29/027 ,  G11C17/14 ,  G11C17/16 ,  G11C17/18 ,  G11C29/02 ,  G11C29/50 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A low voltage programmable electronic fuse structure incorporating a differential sensing scheme is disclosed for integrated circuits. The programming step is performed at about 1.5 times Vdd while the sense operation is performed at Vdd, which limits the resistance variation through the electronic fuse (xF[j]) caused by the sense operation. The magnitude of the current required for sensing is reduced another factor of two because a reference fuse (xF) and the fuse to be programmed (xF[ j]) are coupled in series, whereas during programming only the programmed fuse (xF[j]) limits the programming current. During the sense operation a gating transistor (mNR) emulates the voltage drop across a fuse select transistor (g[j]) for the case of an intact fuse. A circuit and method for characterizing the resistance of the electronic fuse are also disclosed.

    Self-test architecture to implement data column redundancy in ram
    4.
    发明专利
    Self-test architecture to implement data column redundancy in ram 有权
    自我测试架构在RAM中实现数据列冗余

    公开(公告)号：JP2005085458A

    公开(公告)日：2005-03-31

    申请号：JP2004258419

    申请日：2004-09-06

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： EUSTIS STEVEN M ,  MONDAL KRISHNENDU ,  OUELLETTE MICHAEL R ,  ROWLAND JEREMY P

    IPC: G01R31/28 ,  G01R31/00 ,  G06F19/00 ,  G11C29/00 ,  G11C29/12 ,  G11C29/44

    CPC classification number: G11C29/846 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/72 ,  G11C2029/1208

    Abstract: PROBLEM TO BE SOLVED: To provide self-test architectures for implementing data column and row redundancy with a totally integrated self-test and repair capability in a random access memory (RAM), either a dynamic RAM or a static RAM. SOLUTION: The self-architectures are particularly applicable to compileable memories and to embedded RAM with microprocessor or logic chips. The self-architectures uses two passes of self-test of a memory. The first pass of self-test determines the worst failing column, the column with the largest number of unique failing row addresses. After completion of the first pass of self-test, the spare column is allocated to replace the worst failing column. In the second pass of self-test, the BIST collects unique failing row addresses as it does today for memories with spare rows only. At the completion of the second pass of self-test, the spare rows are then allocated. Once the second pass of self-test is completed, the column and unique failing row addresses are transported to the e-fuse macros and permanently stored in the chip. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供自检架构，用于在随机存取存储器（RAM）（动态RAM或静态RAM）中实现全面集成的自检和修复能力的数据列和行冗余。 解决方案：自我架构特别适用于可编程存储器和嵌入式微处理器或逻辑芯片的RAM。 自我架构使用两次记忆自检。 自检的第一次通过确定最差的列，最大数量唯一的失败行地址的列。 自检完成后，备用列被分配以替代最差的故障列。 在第二次自检过程中，BIST收集了唯一的失败行地址，因为它现在只能用于备用行的记忆。 在完成自我测试的第二次通过后，然后分配备用行。 一旦自检的第二次通过完成，列和唯一的故障行地址被传输到电子熔丝宏并永久存储在芯片中。 版权所有（C）2005，JPO＆NCIPI

    Saving content addressable memory power through conditional comparisons
    5.
    发明专利
    Saving content addressable memory power through conditional comparisons 审中-公开
    通过条件比较节省内容可寻址的内存功率

    公开(公告)号：JP2003068085A

    公开(公告)日：2003-03-07

    申请号：JP2002184247

    申请日：2002-06-25

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

    Inventor： CHADWICK THOMAS B ,  GORDON TARL S ,  JASINSKI ERIC ,  NADKARNI RAHUL ,  OUELLETTE MICHAEL R

    IPC: G11C15/04 ,  G11C29/56 ,  G11C29/00

    CPC classification number: G11C15/04

    Abstract: PROBLEM TO BE SOLVED: To provide an address memory (CAM) in which the number of times of pre-charge is reduced and power consumption can be reduced securing high speed operation.
    SOLUTION: A synkline and a matchline are reset to second voltage from a first voltage in accordance with the results of a compare operation of the input data and data in a storage device. When the second voltage appears on the matchline and the first voltage appears on a synkline, it is indicated that the data included in all sub-arrays coincides with input data. When the second voltage appears on the synkline, it is indicated that any data of the sub-arrays does not coincide with input data, or an invalid state in a valid memory cell is indicated, and the synkline is kept at the second voltage. When the first sub-array has data being different from input data, the synkline is kept at the second voltage by the above. Further, while the synkline keeps the second voltage, the matchline is kept at the second voltage.
    COPYRIGHT: (C)2003,JPO

    Abstract translation: 要解决的问题：提供一种地址存储器（CAM），其中预充电次数减少，并且能够降低功率消耗，从而确保高速操作。 解决方案：根据存储设备中的输入数据和数据的比较操作的结果，将synkline和匹配线从第一电压复位到第二电压。 当第二个电压出现在匹配线上，第一个电压出现在同步线上时，表明包括在所有子阵列中的数据与输入数据一致。 当synkline上出现第二个电压时，表示子阵列的任何数据与输入数据不一致，或指示有效存储单元中的无效状态，并且synkline保持在第二电压。 当第一子阵列具有与输入数据不同的数据时，通过上述将同步线保持在第二电压。 此外，当同步线保持第二电压时，匹配线保持在第二电压。

    LOW VOLTAGE PROGRAMMABLE eFUSE WITH DIFFERENTIAL SENSING SCHEME
    6.
    发明申请
    LOW VOLTAGE PROGRAMMABLE eFUSE WITH DIFFERENTIAL SENSING SCHEME 审中-公开
    具有差分感应方案的低电压可编程电源

    公开(公告)号：WO2006028946A3

    公开(公告)日：2007-02-15

    申请号：PCT/US2005031246

    申请日：2005-09-01

    Applicant: IBM ,  OUELLETTE MICHAEL R ,  WISSEL LARRY

    Inventor： OUELLETTE MICHAEL R ,  WISSEL LARRY

    IPC: H01H37/76

    CPC classification number: G11C29/027 ,  G11C17/14 ,  G11C17/16 ,  G11C17/18 ,  G11C29/02 ,  G11C29/50 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A low voltage programmable electronic fuse structure incorporating a differential sensing scheme is disclosed for integrated circuits. The programming step is performed at about 1.5 times Vdd while the sense operation is performed at Vdd, which limits the resistance variation through the electronic fuse (xF[j]) caused by the sense operation. The magnitude of the current required for sensing is reduced another factor of two because a reference fuse (xF) and the fuse to be programmed (xF[ j]) are coupled in series, whereas during programming only the programmed fuse (xF[j]) limits the programming current. During the sense operation a gating transistor (mNR) emulates the voltage drop across a fuse select transistor (g[j]) for the case of an intact fuse. A circuit and method for characterizing the resistance of the electronic fuse are also disclosed.

    Abstract translation: 针对集成电路公开了一种结合差分感测方案的低压可编程电子熔丝结构。 在Vdd执行感测操作时，以Vdd的大约1.5倍执行编程步骤，这限制了由感测操作引起的电子熔丝（xF [j]）的电阻变化。 由于参考保险丝（xF）和要编程的熔丝（xF [j]）串联耦合，传感所需电流的幅度减小了另外两倍，而在编程期间仅编程熔丝（xF [j] ）限制了编程电流。 在感测操作期间，门控晶体管（mNR）在完整的熔丝的情况下模拟保险丝选择晶体管（g [j]）上的电压降。 还公开了用于表征电子熔断器的电阻的电路和方法。

    ARBITRIERUNG ZUR SPEICHERDIAGNOSE
    9.
    发明专利
    ARBITRIERUNG ZUR SPEICHERDIAGNOSE 未知

    公开(公告)号：DE102016204623A1

    公开(公告)日：2016-09-29

    申请号：DE102016204623

    申请日：2016-03-21

    Applicant: IBM

    Inventor： BUSI ARAVINDAN J ,  GORMAN KEVIN W ,  HANAGANDI DEEPAK I ,  NARAYAN KIRAN K ,  OUELLETTE MICHAEL R

    IPC: G06F11/22

    Abstract: Es werden eine serielle Arbitrierung zur Speicherdiagnose und Verfahren davon bereitgestellt. Das Verfahren weist ein paralleles Ausführen eines integrierten Selbsttests (BIST) in einer Mehrzahl von Speichern auf. Bei Erkennen eines fehlerhaften Speichers aus der Mehrzahl von Speichern weist das Verfahren außerdem ein Auslösen einer Arbitrierungslogik auf, um Daten des fehlerhaften Spleichers an ein Chip-Pad zu verschieben.

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