公开(公告)号：US6363023B2

公开(公告)日：2002-03-26

申请号：US79295901

申请日：2001-02-26

Applicant: IBM

Inventor： ANDERSEN JOHN E ,  OUELLETTE MICHAEL R

IPC: G11C7/06 ,  G11C11/419 ,  G11C7/02

CPC classification number: G11C11/419 ,  G11C7/065

Abstract: A device and method is provided for reducing power consumption in memory devices. The preferred embodiment reduces power consumption by providing a sense amplifier that reduces power consumption while providing high performance. In the preferred embodiment the sense amplifier comprises a bi-directional sense amp that is configurable for use on low power static random access memory (SRAM) devices. The bi-directional sense amp allows the same sense amp to be used for both read and write operations on the memory cells. The preferred embodiment sense amp facilitates the use of differential data buses, further reducing power consumption while providing high performance. Thus, the preferred embodiment bi-directional differential sense amp reduces the device size and complexity, reducing power consumption while providing high performance memory access.

Abstract translation: 提供了一种用于降低存储器件中的功耗的装置和方法。 优选实施例通过提供在提供高性能的同时降低功耗的读出放大器来降低功耗。 在优选实施例中，读出放大器包括可配置用于低功率静态随机存取存储器（SRAM）器件的双向读出放大器。 双向读出放大器允许将相同的感测放大器用于存储器单元上的读取和写入操作。 优选实施例的感测放大器有助于使用差分数据总线，进一步降低功耗，同时提供高性能。 因此，优选实施例的双向差分检测放大器降低了器件尺寸和复杂性，降低了功耗，同时提供了高性能的存储器访问。

公开(公告)号：DE3484286D1

公开(公告)日：1991-04-25

申请号：DE3484286

申请日：1984-06-08

Applicant: IBM

Inventor： ANDERSEN JOHN E ,  MESSINA BENEDICTO U ,  PETROSKY JOSEPH A ,  SILKMAN WILLIAM D

IPC: G06F12/00 ,  G06F7/02 ,  G06F12/02 ,  G06F12/08 ,  G06F17/30 ,  G06F15/40

Abstract: A directory memory having simultaneous writing and bypass capabilities. A data output bit (DB n ) from a respective memory cell of a memory array is applied to a control input of a first differential amplifier (63, 66), while comparison input data is applied to inputs of a second differential amplifier (64, 65). The outputs of corresponding transistors of the two differential amplifiers are connected together. Current switch transistors (77, 78), operated in response to a bypass select signal, supply current only to one or the other of the two differential amplifiers. The differential output signal produced across the commonly connected outputs of the two differential amplifier circuits is buffered and amplified with a push-pull output circuit (62, 87).