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    System for detection of data time interval measurement
    2.
    发明授权
    System for detection of data time interval measurement 失效
    用于检测数据时间间隔测量的系统

    公开(公告)号：US3631422A

    公开(公告)日：1971-12-28

    申请号：US3631422D

    申请日：1969-02-03

    Applicant: IBM

    Inventor： KRAJEWSKI WILLIAM F ,  PADALINO MARCO ,  PAULSON DAVID H

    IPC: H03M5/14 ,  G06K7/00 ,  G11B20/14 ,  H04L25/49 ,  G11B5/04

    CPC classification number: G11B20/1423

    Abstract: A system is provided in which data processed in digitally encoded form is detected using an inverse algorithm of the encoding process and the predictable nature of errors which may be introduced by the processing media. In one example, a measurement of the time interval between each adjacent pair of data signal transitions derived from a magnetic recording media is adjusted to compensate for speed variations of the recording media, and the adjusted measurement is categorized according to the predictable nature of bit shift introduced by the recording media. Logic circuitry responds to each categorized time interval measurement to determine the data denoted thereby in terms of data detected from the immediately preceding time interval.

    Magnetic record with servo track perpendicular to information track
    3.
    发明授权
    Magnetic record with servo track perpendicular to information track 失效
    具有伺服轨迹的磁记录信息跟踪

    公开(公告)号：US3614756A

    公开(公告)日：1971-10-19

    申请号：US3614756D

    申请日：1970-01-21

    Applicant: IBM

    Inventor： MCINTOSH ROBERT P ,  PADALINO MARCO

    IPC: G11B5/33 ,  G05D3/20 ,  G11B5/127 ,  G11B5/48 ,  G11B5/596 ,  G11B5/28 ,  G11B5/38 ,  G11B21/08

    CPC classification number: G11B5/4886 ,  G05D3/20 ,  G11B5/59633 ,  G11B5/5965

    Abstract: The invention relates to a servosystem used in a random access disk memory system which comprises a magnetic disk having servo tracks recorded such that the magnetic domains within the servo tracks are aligned radially from the center of the disk and data tracks which have the magnetic domains are aligned concentrically about the center of the disk, and a transducer capable of developing a data signal as a function of the rate of change of the magnetic flux associated with the data tracks and a servo signal generated by the magnitude of the absolute flux magnitude that it presented to the transducer by the transducer''s relationship to the servo tracks on the magnetic disk, the servo signal and the data signals being generated either simultaneously or alternately in the magnetic transducer.

    MAGNETICALLY RECORDING AND REPRODUCING INFORMATION
    5.
    发明专利
    MAGNETICALLY RECORDING AND REPRODUCING INFORMATION 未知

    公开(公告)号：GB1277177A

    公开(公告)日：1972-06-07

    申请号：GB125671

    申请日：1971-01-11

    Applicant: IBM

    Inventor： MCINTOSH ROBERT PAUL ,  PADALINO MARCO

    IPC: G11B5/33 ,  G05D3/20 ,  G11B5/127 ,  G11B5/48 ,  G11B5/596

    Abstract: 1277177 Magnetic recording and playback INTERNATIONAL BUSINESS MACHINES CORP 11 Jan 1971 [21 Jan 1970] 1256/71 Heading G5R A magnetic transducer 2 has the usual record/playback gap 21 and also a portion 22 sensitive to magnetic flux directed transversely of the gap 21 so as to generate a signal indicative of the intensity of that flux. This signal controls the aligning of the transducer 2 with a data track on a magnetic disc in which a layer of relatively low coercivity carrying the data tracks overlies a layer of relatively high coercivity in which concentric control tracks are magnetized alternately in opposite radial directions so that the boundary between two control tracks underlies the centre line of a data track (Figs. 3 and 4, not shown). The disc may be divided into sectors carrying alternately data and control recordings (Figs. 5 and 6, not shown). The flux-sensitive head portion 22 may exhibit the Hall effect.

    7.
    发明专利
    未知

    公开(公告)号：DE1774505A1

    公开(公告)日：1972-03-23

    申请号：DE1774505

    申请日：1968-07-04

    Applicant: IBM

    Inventor： PADALINO MARCO ,  FRANK KROJEWSKI WILLIAM ,  NAGAKURA HIROSHI

    IPC: G11B20/14 ,  G11B5/02

    Abstract: 1,165,658. Data storage. INTERNATIONAL BUSINESS MACHINES CORP. 24 June, 1968 [17 July, 1967], No. 30073/68. Heading G4C. In a data signalling system, a bit of one kind (1) is represented by a transition near the centre of a bit " cell " and a bit of the opposite kind (0) by a transition near the start of a bit " cell " except when it follows a bit of the one kind when it is represented by no transition. A " transmitter " converts data into this form for transmission or recording on to a magnetic tape, disc or drum store. A " receiver " converts data from this form after reception or reading from the store. Transmitter (recording), Fig. 1.-Parallel input data 12 is serialized in register 10, each bit being gated at 16, 18 by an " EVEN " clock pulse to set or reset a trigger 34 according as the bit is 0 or 1. The " EVEN " clock pulses are produced alternately with " ODD " clock pulses by an oscillator-driven trigger 22, one of each type of pulse per bit period. A write circuit 38 produces a transition for each pulse it receives from an OR 36 which receives a pulse from AND 16 at " EVEN " clock pulse time for each 1 bit and a pulse from an AND 42 at " ODD " clock pulse time for each 0 bit not immediately preceded by a 1. Receiver (reading), Fig. 3.-A processor 60 including an amplifier, filter, differentiator, limiter and shaper produces a pulse for each positive and negative peak of the received (read) waveform, the pulses being delayed and sharpened at 98 prior to gating, at 94, of the pulses representing 1 bits, into a serial-toparallel converter 106. A ramp generator 68 produces two ramps per bit period and is kept in sync. with the data from processor 60 by an error detector 66 which adjusts the ramp frequency. A threshold detector 72 responds to each positive and negative peak (Π3 volts) of the ramp to switch a trigger 88, and also control ramp flyback via a delay 78. A threshold detector 74 supplies a pulse to an OR 92 as long as the ramp is above +2 volts or below -2 volts. The OR 92 also receives the set output of trigger 88 thus producing a pulse of duration about 60% of the bit period to gate any 1 bit pulse at AND 94 to converter 106. Any 0 bit pulse (i.e. representing a 0 not immediately following a 1) is gated through an AND 86 as shown. The trigger 88 may be phase-locked to a reference.

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