公开(公告)号：GB2454598B

公开(公告)日：2012-04-18

申请号：GB0822217

申请日：2008-12-05

Applicant: IBM

Inventor： DORSCH RAINER ,  GRASSI MICHAEL ,  HELMS MARKUS ,  PANDEY KULWANT M ,  SCHLIPF THOMAS

IPC: H04L12/56

公开(公告)号：GB2454598A

公开(公告)日：2009-05-13

申请号：GB0822217

申请日：2008-12-05

Applicant: IBM

Inventor： DORSCH RAINER ,  GRASSI MICHAEL ,  HELMS MARKUS ,  PANDEY KULWANT M ,  SCHLIPF THOMAS

IPC: H04L12/56

Abstract: An apparatus and method is disclosed for transferring data packets synchronously in a credit controlled manner from a transmitter (10, fig. 1, not shown) to a receiver (20,fig. 1), wherein the receiver transfers a credit to the transmitter and the transmitter transfers said packets to the receiver in response to said credit showing available buffer space in a data buffer (26,fig.1) of the receiver. The data buffer (26) is configured to comprise a virtually unlimited buffer space offering infinite credits. The receiver creates a credit signal (CI1, C12, CI3, C14, DC12, DCI3), which shows, independent from a physical size of the data buffer (26), a virtual buffer space giving credit for just one further data packet to be received at a time from the transmitter, and transfers the credit signal to the transmitter, wherein the receiver component sends a credit (e.g. CI1) for a following packet as soon as it starts receiving a current packet, but can delay sending the credit for a certain time (e.g. DC12, DC13) if conditions in the data buffer demand a delay. The delayed credit forces the transmitter to insert a gap (e.g. FG1, FG2) between packets. The timing of the normal credit CI1 ensures that through put is not compromised.