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    A METHOD FOR PROVIDING REDUNDANCY FOR CHANNEL ADAPTER FAILURE
    1.
    发明专利
    A METHOD FOR PROVIDING REDUNDANCY FOR CHANNEL ADAPTER FAILURE 未知

    公开(公告)号：AU2003226784A1

    公开(公告)日：2003-10-27

    申请号：AU2003226784

    申请日：2003-04-04

    Applicant: IBM

    Inventor： SCHLIPF THOMAS ,  BAYER GERD KONRAD ,  ECKERT WOLFGANG ,  HELMS MARKUS ,  MAERGNER JUERGEN ,  RAISCH CHRISTOPH ,  THEURICH KLAUS

    IPC: G06F13/00 ,  H04L45/24 ,  H04L45/28 ,  H04L45/58 ,  H04L12/56

    Abstract: The invention relates to a method for providing improved reliability of any node attaching to an InfiniBand fabric, the method comprising the steps of: a) providing a first and a second physical Channel Adapter having a first and a second number of ports, b) providing program means for registering the first and second physical Channel Adapters as one logical Channel Adapter having a number of first and second ports, c) providing first and second caching means for storing first and second control information for the first and second Channel Adapter, d) providing system memory means for storing first and second control information, and e) providing means for copying the first control information from the system memory to the second caching means in case of a failure of the first Channel Adapter and for initiating an Automatic Path Migration from the first number of ports to the second number of ports.

    Method for producing a vector indicating the measured utilization of a piece of hardware.
    4.
    发明专利
    Method for producing a vector indicating the measured utilization of a piece of hardware. 未知

    公开(公告)号：GB2454599A

    公开(公告)日：2009-05-13

    申请号：GB0822308

    申请日：2008-12-08

    Applicant: IBM

    Inventor： HELMS MARKUS

    IPC: G06F11/34

    Abstract: Disclosed is a method and apparatus 10 for measuring the utilization and/or throughput of a hardware device 02. The method has the steps of, sampling indicators from the device under measurement every defined number (n) of cycles, the indicators are represented by bits with values of "0" for a non-busy state and "1" for a busy state. The method uses the sampled bits to generate a vector of a defined number (k) of indicators, so that the vector keeps a history of sampled busy vs. non-busy states. Every defined number of cycles when a new indicator is sampled and taken-up in the vector, the oldest indicator in the vector is kicked out. The vector is uses to generate a sum over all bits kept in the vector, said sum indicating a relative utilization of said device. The sampling period may be set using a counter 01 that creates a sampling pulse every n cycles, with n being a prime number. The vector may be generated by K flip-flops 05 in a shift register 04.

    5.
    发明专利
    未知

    公开(公告)号：AT468562T

    公开(公告)日：2010-06-15

    申请号：AT01128821

    申请日：2001-12-04

    Applicant: IBM

    Inventor： BAYER GERD KONRAD ,  ECKERT WOLFGANG ,  HELMS MARKUS ,  MAERGNER JUERGEN ,  RAISCH CHRISTOPH ,  SCHLIPF THOMAS ,  THEURICH KLAUS

    IPC: G06F13/38 ,  H04L12/46

    Abstract: A method and apparatus relates to hardware-to-hardware data transmission in computer systems, and in particular, it relates to method and system for operating I/O adapters attaching either one or more computing devices to an I/O periphery, to a network, or to other computing devices. It is proposed to operate a memory local to the network coupling adapter as a cache memory relative to a system memory associated with the one or more computing devices for storing transmission control information.

    Request filtering in multi-stage arbiter circuitry to reduce latency
    6.
    发明专利
    Request filtering in multi-stage arbiter circuitry to reduce latency 未知

    公开(公告)号：GB2454818A

    公开(公告)日：2009-05-20

    申请号：GB0822309

    申请日：2008-12-08

    Applicant: IBM

    Inventor： HELMS MARKUS ,  SENTLER DANIEL ,  WALZ MANFRED

    IPC: G06F13/364 ,  G06F13/30

    Abstract: Arbiter circuitry 11 includes at least one request filter 12, a plurality of requestor latches 14, at least two staged arbiters 13 arranged directly behind the requestor latches, and an arbitration result latch 15 arranged behind the arbiters. Request filter 12 is arranged behind the arbitration result latch 15 in a non-timing critical path, e.g. pipeline stage 16. A latency reduction is achieved by avoiding stage latches (06, fig. 1). Moving filter 12 to pipeline stage 16 means that incorrect arbitration results may occur so, preferably, it is possible to rollback incorrect arbitration results. To allow rollback, two-staged grants may be provided, e.g. a preliminary grant (22) in a first cycle and a final grant (24) in a second cycle. Preferably, arbitration circuitry 11 is operated below its maximum throughput capacity. The invention may be applied to processing direct memory access (DMA) requests of input/output (I/O) devices attached to an I/O adapter of a host device having main memory.

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