公开(公告)号：GB1254223A

公开(公告)日：1971-11-17

申请号：GB3197169

申请日：1969-06-25

Applicant: IBM

Inventor： NUSSBAUMER HENRI JEAN ,  PARIS ETIENNE EDOUARD

IPC: H03H17/08 ,  H03H19/00 ,  H04J1/06 ,  H04L7/00 ,  H04L27/00

Abstract: 1,254,223. Active filters; phase lock circuits. INTERNATIONAL BUSINESS MACHINES CORP. 25 June, 1969 [5 July, 1968], No. 31971/69. Heading H3A and H3U. A phase shifter comprising capacitors C1 ... C4 connected to an input 1 via respective input switches S1 ... S4 and to an output 1 11 via respective output switches S5 ... S8 is characterized by the provision of means for varying the relative operating time of corresponding input and output switches to vary the phase shift. A second set of output switches operated at different phases from switches S5 ... S8 may be added to give a different phase output, Fig. 9c (not shown). The circuit may be used in a data transmission system, for locking the phases of the received modulated carrier and the data rate to those of locally generated carrier and clock signals respectively. The carrier lock circuit, Fig. 3, comprises a phase shifter SF2 of the type described fed with the received carrier signal to provide a first input to a phase comparator " LOGIC." The local signal provides a second reference input p and the resulting error output from the comparator is applied to an AND gate together with the output from an oscillator OSC2, to adjust the timing of the output switches of the phase shifter relative to the input switches. The output from the oscillator is fed to a first divider path d3, d4 to operate the input switches, and a second similar divider path is included between the AND gate and the output switches. The dividers may comprise a chain of binary circuits with the necessary outputs taken from different points along the chain. Fig. 6 (not shown). In this Figure, the comparator " LOGIC " is shown to produce further timing pulses which vary the timing of output pulses from divider d5, d6. The data lock circuit, Fig. 9a (not shown), uses a similar control circuit in which a phase shifter (SF4) is fed with data signals and is controlled by an oscillator (OSC) via a divider (d 11 ). A modification, Fig. 9b (not shown), employs the phase shifter of Fig. 9c (not shown), to give phase displaced outputs.

公开(公告)号：GB1187688A

公开(公告)日：1970-04-15

申请号：GB4797568

申请日：1968-10-10

Applicant: IBM

Inventor： NUSSBAUMER HENRI JEAN ,  PARIS ETIENNE EDOUARD

IPC: H04L7/00 ,  H04L7/02 ,  H04L7/027

Abstract: 1,187,688. Digital transmission systems. INTERNATIONAL BUSINESS MACHINES CORP. 10 Oct., 1968 [8 Nov., 1967; 9 Nov., 1967; 8 Dec., 1967], No. 47975/68. Heading H4P. Synchronizing signals are derived from a signal which has digital data signals at times tn, t 1 n and non-significant signals at all other times. Whenever the signal has a preset amplitude a sync. pulse is generated. This amplitude occurs at tn, t 1 n and may also occur at other times. The receiver prevents sync. pulses occurring at times other than tn, t 1 n from effecting the oscillator. In one embodiment, the received signal contains binary data and passes to a subtraction unit S, Fig. 3, via rectifiers 31, 32 and delay 33 whose period t = t 1 n-tn. The output of S is a signal which has zero amplitude whenever the preset amplitude is detected, and is passed via monostables SS1, SS2 and inverter I1 to OR gate 01 which gives pulses p whenever the output of S is zero. Gate 01 feeds oscillator Plo which clock pulses of period T, T being the recurrence period of both tn and t 1 n. Gate A1 is inhibited by the output of monostable SS3, fed by the clock pulses, so that any sync. pulses occurring at times other than tn, t 1 n cannot reach Plo. During unitial synchronization, when a special start signal is received, a signal on Dem maintains A1 enabled. In a second embodiment, Fig. 5 (not shown), the digital signals may take any of four preset valves. Rectifiers 31, 32, Fig. 3, are additionally connected to two weighted subtraction units whose outputs pass to an EXCL-OR gate which feeds a second EXCL-OR gate inserted between S and SQ: Another arrangement, Fig. 6, in which there is no initial sync. signal, uses a series of delay units, each of period T, to which the rectified received signal is fed. An AND gate, A3 is fed as shown and emits a pulse about the times tn, t 1 n, Fig. 2b (not shown), since at other times at least one input to the gate is likely to be zero. The output of the gate is used to gate appropriate pulses of signal p to the oscillator. Alternatively, Fig. 7 (not shown), the delays may be replaced by a single delay T fed via an AND gate with the rectified signal, the delay giving synchronizing pulses which are also fed back to the gate. The delay may comprise a shift register, and a threshold unit may precede the AND gate, Fig. 8 (not shown). In another embodiment, Fig. 11, there is a unit 111 generally similar to Fig. 3, and in addition a weighted adder 112 and a unit 113 containing an adder, a delay, and a subtractor. The outputs of both 112 and 113 are zero only about tn, t 1 n, and are fed to analog adder AD3 together with the clock signal from PL0. The resulting signal c is zero at times t 1 n and attenuates the unwanted pulses from 111, the wanted pulses synchronizing the oscillator PL0. Where 4-level signals are received, Fig. 13 (not shown), units 112, 113, Fig. 11, are replaced by weighted adders Ad4, Ad5, the lesser of the two outputs passing to the gate Ad3. In a final embodiment, Fig. 15, the received signal is fed direct and via a delay t to a unit 151, which outputs the lesser of the two signals. This output passes to capacitor C1 to Cn, switched in sequentially for a period T/n by unit Seq. A capacitor charges slowly when switched in unless the output of 151 is zero, when the capacitor rapidly discharges. Since 151 gives zero output at random, but never at the times t 1 n, after several periods T one capacitor will have a charge higher than the others, so identifying the time t 1 n.