公开(公告)号：US3619502A

公开(公告)日：1971-11-09

申请号：US3619502D

申请日：1969-09-03

Applicant: IBM

Inventor： CROISIER ALAIN ,  NUSSBAUMER HENRI JEAN

IPC: H04M11/06 ,  H04L25/48 ,  H04L25/497 ,  H04M11/00 ,  H04L27/24

CPC classification number: H04L25/497

Abstract: A method for directly generating a data representing signal corresponding to a single sideband of a data modulated carrier signal and suitable for transmission over a limited frequency network. The signal comprises the summation of a number of bit representing pulse sequences, each sequence including a central bit indicating pulse and both preceding and following echo pulses. The pulses are generated by digital techniques and their spacing and amplitude are so selected that after passing through a low-pass filter, the resultant signal has no frequency components outside of a predetermined frequency band.

公开(公告)号：US3577082A

公开(公告)日：1971-05-04

申请号：US3577082D

申请日：1969-03-05

Applicant: IBM

Inventor： LAUTIER ALEX HONORE ,  NUSSBAUMER HENRI JEAN ,  PIERRET JEAN MARC

IPC: H04B1/68 ,  H04L27/06 ,  H04B1/16

CPC classification number: H04B1/68 ,  H04L27/066

Abstract: A phase synchronizing device for the carrier of a single sideband transmission system. Two pilot frequencies are transmitted with the synchronization signal and are decoded at the receiver to provide a signal indicating the correct phase of the demodulating carrier signal. The transmitted carrier signal controls the frequency of an oscillator and the initial phase of the regenerated carrier signal is set a the start of reception by the decoded pilot signals.

公开(公告)号：DE2324924A1

公开(公告)日：1974-01-17

申请号：DE2324924

申请日：1973-05-17

Applicant: IBM

Inventor： NUSSBAUMER HENRI JEAN

IPC: G06F7/60 ,  G06F7/64 ,  G06J1/00

公开(公告)号：DE2317597A1

公开(公告)日：1973-11-15

申请号：DE2317597

申请日：1973-04-07

Applicant: IBM

Inventor： LAUTIER ALEX ,  MADDENS FRANCIS PAUL ,  NUSSBAUMER HENRI JEAN ,  PIERRET JEAN MARC

IPC: H04B3/06 ,  H03H17/00 ,  H03H17/08 ,  H04L27/01 ,  H04L27/22

Abstract: A self-adjustable equalizer for a phase modulation communication system in which the equalizer output signal s is sampled at the modulation rate and weighted by a factor proportional to envelope amplitude distortion dR/R, R being the envelope amplitude at given instants and the product sdR/R being the adjustment control signal. In the preferred embodiment the product of the sign of s and the sign of dR serves as the control or error signal. One implementation frequency translates the equalizer output signal and compares the amplitude of the translated signal with a reference at given instants to determine the sign of dR which is eventually multiplied by the sign of s.

公开(公告)号：GB1187688A

公开(公告)日：1970-04-15

申请号：GB4797568

申请日：1968-10-10

Applicant: IBM

Inventor： NUSSBAUMER HENRI JEAN ,  PARIS ETIENNE EDOUARD

IPC: H04L7/00 ,  H04L7/02 ,  H04L7/027

Abstract: 1,187,688. Digital transmission systems. INTERNATIONAL BUSINESS MACHINES CORP. 10 Oct., 1968 [8 Nov., 1967; 9 Nov., 1967; 8 Dec., 1967], No. 47975/68. Heading H4P. Synchronizing signals are derived from a signal which has digital data signals at times tn, t 1 n and non-significant signals at all other times. Whenever the signal has a preset amplitude a sync. pulse is generated. This amplitude occurs at tn, t 1 n and may also occur at other times. The receiver prevents sync. pulses occurring at times other than tn, t 1 n from effecting the oscillator. In one embodiment, the received signal contains binary data and passes to a subtraction unit S, Fig. 3, via rectifiers 31, 32 and delay 33 whose period t = t 1 n-tn. The output of S is a signal which has zero amplitude whenever the preset amplitude is detected, and is passed via monostables SS1, SS2 and inverter I1 to OR gate 01 which gives pulses p whenever the output of S is zero. Gate 01 feeds oscillator Plo which clock pulses of period T, T being the recurrence period of both tn and t 1 n. Gate A1 is inhibited by the output of monostable SS3, fed by the clock pulses, so that any sync. pulses occurring at times other than tn, t 1 n cannot reach Plo. During unitial synchronization, when a special start signal is received, a signal on Dem maintains A1 enabled. In a second embodiment, Fig. 5 (not shown), the digital signals may take any of four preset valves. Rectifiers 31, 32, Fig. 3, are additionally connected to two weighted subtraction units whose outputs pass to an EXCL-OR gate which feeds a second EXCL-OR gate inserted between S and SQ: Another arrangement, Fig. 6, in which there is no initial sync. signal, uses a series of delay units, each of period T, to which the rectified received signal is fed. An AND gate, A3 is fed as shown and emits a pulse about the times tn, t 1 n, Fig. 2b (not shown), since at other times at least one input to the gate is likely to be zero. The output of the gate is used to gate appropriate pulses of signal p to the oscillator. Alternatively, Fig. 7 (not shown), the delays may be replaced by a single delay T fed via an AND gate with the rectified signal, the delay giving synchronizing pulses which are also fed back to the gate. The delay may comprise a shift register, and a threshold unit may precede the AND gate, Fig. 8 (not shown). In another embodiment, Fig. 11, there is a unit 111 generally similar to Fig. 3, and in addition a weighted adder 112 and a unit 113 containing an adder, a delay, and a subtractor. The outputs of both 112 and 113 are zero only about tn, t 1 n, and are fed to analog adder AD3 together with the clock signal from PL0. The resulting signal c is zero at times t 1 n and attenuates the unwanted pulses from 111, the wanted pulses synchronizing the oscillator PL0. Where 4-level signals are received, Fig. 13 (not shown), units 112, 113, Fig. 11, are replaced by weighted adders Ad4, Ad5, the lesser of the two outputs passing to the gate Ad3. In a final embodiment, Fig. 15, the received signal is fed direct and via a delay t to a unit 151, which outputs the lesser of the two signals. This output passes to capacitor C1 to Cn, switched in sequentially for a period T/n by unit Seq. A capacitor charges slowly when switched in unless the output of 151 is zero, when the capacitor rapidly discharges. Since 151 gives zero output at random, but never at the times t 1 n, after several periods T one capacitor will have a charge higher than the others, so identifying the time t 1 n.

公开(公告)号：DE2208367A1

公开(公告)日：1973-10-25

申请号：DE2208367

申请日：1972-02-23

Applicant: IBM

Inventor： HUREL DIDIER GEORGES ,  NUSSBAUMER HENRI JEAN ,  PATURET JACQUES NOEL ,  BATHERET PIERRE HENRI

IPC: H04J1/08 ,  H04L27/30 ,  H04Q1/457

Abstract: 1318499 Selective signalling INTERNATIONAL BUSINESS MACHINES CORP 28 Jan 1972 [3 March 1971] 4051/72 Heading H4 K1H3B1 A receiver for decoding multifrequency signals of which each component frequency is taken from a different predetermined group of frequencies has a different channel for each group of frequencies, each channel including a majority circuit arranged to generate a binary signal representative of the amplitude of a majority of a predetermined number of samples of the frequency signal in the channel, and means for determining the rate of zero crossings of a sequence of the binary signals to determine the frequency of the signal in the channel. The input is passed via an A/D converter to a digital transversal filter which is time-multiplexed with the factors required to obtaining the different groups of frequencies. The filter output goes to the channels mentioned. Each channel consists of a majority circuit followed by a frequency detector. The majority circuit consists of a peak clipper, a sampler and a shift register in series, the shift register stages being connected in parallel to a summer the output of which is compared with a reference value to obtain the binary signal. The majority circuit thus eliminates noise. The frequency detector counts clock pulses for 16 periods of the binary signal (which is a square wave), the count being decoded to identify the component frequency. The decoder output from the channels are combined in a final decoder. Confirmation logic responsive to the channel decoders checks the presence of component frequencies according to simultaneous presence or order of appearance criteria, as appropriate.

公开(公告)号：DE2232757A1

公开(公告)日：1973-03-01

申请号：DE2232757

申请日：1972-07-04

Applicant: IBM

Inventor： MONROLIN JEAN LOUIS ,  NUSSBAUMER HENRI JEAN ,  PIERRET JEAN MARC

IPC: H04B3/06 ,  H03H15/00 ,  H03H17/00 ,  H03H21/00 ,  H03K5/00 ,  H04L7/02 ,  H04L25/03 ,  H04L25/04

公开(公告)号：GB1254223A

公开(公告)日：1971-11-17

申请号：GB3197169

申请日：1969-06-25

Applicant: IBM

Inventor： NUSSBAUMER HENRI JEAN ,  PARIS ETIENNE EDOUARD

IPC: H03H17/08 ,  H03H19/00 ,  H04J1/06 ,  H04L7/00 ,  H04L27/00

Abstract: 1,254,223. Active filters; phase lock circuits. INTERNATIONAL BUSINESS MACHINES CORP. 25 June, 1969 [5 July, 1968], No. 31971/69. Heading H3A and H3U. A phase shifter comprising capacitors C1 ... C4 connected to an input 1 via respective input switches S1 ... S4 and to an output 1 11 via respective output switches S5 ... S8 is characterized by the provision of means for varying the relative operating time of corresponding input and output switches to vary the phase shift. A second set of output switches operated at different phases from switches S5 ... S8 may be added to give a different phase output, Fig. 9c (not shown). The circuit may be used in a data transmission system, for locking the phases of the received modulated carrier and the data rate to those of locally generated carrier and clock signals respectively. The carrier lock circuit, Fig. 3, comprises a phase shifter SF2 of the type described fed with the received carrier signal to provide a first input to a phase comparator " LOGIC." The local signal provides a second reference input p and the resulting error output from the comparator is applied to an AND gate together with the output from an oscillator OSC2, to adjust the timing of the output switches of the phase shifter relative to the input switches. The output from the oscillator is fed to a first divider path d3, d4 to operate the input switches, and a second similar divider path is included between the AND gate and the output switches. The dividers may comprise a chain of binary circuits with the necessary outputs taken from different points along the chain. Fig. 6 (not shown). In this Figure, the comparator " LOGIC " is shown to produce further timing pulses which vary the timing of output pulses from divider d5, d6. The data lock circuit, Fig. 9a (not shown), uses a similar control circuit in which a phase shifter (SF4) is fed with data signals and is controlled by an oscillator (OSC) via a divider (d 11 ). A modification, Fig. 9b (not shown), employs the phase shifter of Fig. 9c (not shown), to give phase displaced outputs.

公开(公告)号：GB1271753A

公开(公告)日：1972-04-26

申请号：GB4092669

申请日：1969-08-15

Applicant: IBM

Inventor： CROISIER ALAIN ,  NUSSBAUMER HENRI JEAN

IPC: H04M11/06 ,  H04L25/48 ,  H04L25/497 ,  H04M11/00

Abstract: 1,271,753. Digital transmission systems. INTERNATIONAL BUSINESS MACHINES CORP. 15 Aug., 1969 [4 Sept., 1968], No. 40926/69. Addition to 1,154,648. Heading H4P. In a digital transmission system each digital pulse, of duration T, is represented by a pulse sequence comprising a main pulse with two " echo " pulses following and preceding it. Successive sequences overlap, and the system is so designed that the resulting sequence is a signal (Sin (#t/2D).Cos 2#ft)/t, where T=pD (p is integral), and f=(2n-1)/4D. At the receiver this signal is demodulated with a frequency f+1/4D, the demodulated signal being sampled at a rate 1/T. The main pulses may be multi-level signals. In an example in which n = 2 and p = 1, binary data is passed to a 3-bit shift register stepped at bit rate. The parallel output of the register is selectively passed via gates, enabled by three bit-rate time-staggered clock trains, to a circuit which weights its inputs and presents a signal which, after low-pass filtering, has the waveform defined above.

公开(公告)号：GB1268462A

公开(公告)日：1972-03-29

申请号：GB1777770

申请日：1970-04-14

Applicant: IBM

Inventor： NUSSBAUMER HENRI JEAN

IPC: H04L25/48 ,  H04L25/497

Abstract: 1,268,462. Digital transmission systems. INTERNATIONAL BUSINESS MACHINES CORP. 14 April, 1970 [14 April, 1969], No. 17777/70. Heading H4P. In a data transmission system wherein each primary digit is represented by a sequence S comprising a main signal pulse and a predetermined number of preceding and following echo pulses at determined intervals, for each sequence, a series S 1 is generated comprising symmetrical pulses of the form which is summed with the corresponding sequence S and passed through a low pass filter producing a signal, to be transmitted, of a form capable of being demodulated in a conventional device operating at the data repetition rate Ts. The transmitter includes a generator of elementary signals representing data elements, which are received by a register having a number of positions determined by the number of weighted pulses and/or time duration of each signal, a means for generating the series S 1 , and an analogue adder under the control of clock signals which produces a corresponding signal amplitude in respect the values obtaining at the input and/or the positions in the register. Alternate signals may be inverted. The transmitted signal is substantially identical to a frequency modulated signal which may be received by a conventional f.m. demodulating device. Sequences A, B of main and echo signals S representative of individual data elements are shown in the upper two lines of Fig. 1, B being shown inverted and the value of each element being represented by the amplitude. A signal of the form S 1 is generated for each group, that for A being shown in line 6 which signals have an amplitude of 0À707 A max. Each group of signals S 1 is added to the corresponding group S in an analogue adder which after passing through a low pass filter gives a signal of digital type which may be transmitted and which is substantially identical to a f.m. signal. Arrangements for generating and combining the signals are described in the Specification.