公开(公告)号：JP2007200292A

公开(公告)日：2007-08-09

申请号：JP2006346754

申请日：2006-12-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： JACKSON KATHRYN M ,  HUTTON DAVID S ,  LANGSTON KEITH N ,  PARK KIN MAKU ,  SHUM CHUNG-LUNG K

IPC: G06F12/08

CPC classification number: G06F12/0815 ,  G06F12/0811 ,  G06F12/12

Abstract: PROBLEM TO BE SOLVED: To provide caching where portions of data are stored in slower main memory and are transferred to faster memory between one or more processors and the main memory. SOLUTION: The caching where portions of data are stored in slower main memory and are transferred to faster memory between one or more processors and the main memory. The cache is such that an individual cache system must communicate to other associated cache systems, or check with such cache systems, to determine if the cache systems contain a copy of a given cached location prior to or upon modification or appropriation of data at a given cached location. The cache further includes provisions for determining when the data stored in a particular memory location may be replaced. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供高速缓存，其中部分数据存储在较慢的主存储器中，并被传送到一个或多个处理器和主存储器之间的更快的存储器。 解决方案：缓存数据的一部分存储在较慢的主存储器中，并被传送到一个或多个处理器和主存储器之间的更快的存储器。 缓存使得单个缓存系统必须与其他相关联的高速缓存系统进行通信，或者与这种高速缓存系统进行检查，以确定高速缓存系统是否在给定的缓存系统之前或之后修改或占用数据时包含给定缓存位置的副本 缓存位置。 高速缓存还包括用于确定何时可以替换存储在特定存储器位置中的数据的规定。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2000029857A

公开(公告)日：2000-01-28

申请号：JP11471499

申请日：1999-04-22

Applicant: IBM

Inventor： CHARLES F WEBB ,  DEAN G BAYER ,  MARK S FARRELL ,  BARRY W CRAN ,  PARK KIN MAKU ,  JENNIFER A NAVARO

IPC: G06F15/177 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/52

Abstract: PROBLEM TO BE SOLVED: To provide a system serialization method by the early release of individual processors by generating a system standstill request and the request of the updating of a global resource by the processor, responding to the request and buffering the request in the processor during the processing. SOLUTION: Plural CPUs 210 and 211 in a system respectively execute an instruction from a simple instruction set and the instruction from a complicated instruction set in the execution controller 243 of hardware control. The respective CPUs 210 and 211 generate the system standstill request and the request of the updating of the global resource and respond to the request. Then, during the processing, the system standstill request and the request of the updating of the global resource are buffered in one or more of the CPUs 210 and 211. A system operation controller provided with a system serialization controller 220 or the like instructs the updating the global resource.

公开(公告)号：JP2000010942A

公开(公告)日：2000-01-14

申请号：JP11473199

申请日：1999-04-22

Applicant: IBM

Inventor： CHARLES F WEBB ,  DEAN G BAYER ,  MARK S FARRELL ,  BARRY W CRAN ,  PARK KIN MAKU ,  JENNIFER A NAVARO ,  TIMOTHY J SLEEGEL

IPC: G06F9/52 ,  G06F9/318 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To obtain a system which performs system serialization by early releasing of a processor by buffering a system standstill request and a request for updating on the processor. SOLUTION: Plural processors are included in this system and respective processors generates system standstill requests and requests to update global resources and responds to the requests. The system standstill request and the request for updating are buffered by one or plural processors. Then a system operation controller including a storage device controller SC 212 and a system serializing a controller 220 indicates the updating of the global resources. The global resources include an address conversion table entry and a protection key.