公开(公告)号：JP2000029684A

公开(公告)日：2000-01-28

申请号：JP11475699

申请日：1999-04-22

Applicant: IBM

Inventor： MARK A CHECK ,  RONALD M SMITH ,  JOHN S RIPTY ,  ERIK M SCHWARZ ,  TIMOTHY J SLEEGAL ,  CHARLES F WEBB

IPC: G06F9/355 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To support a high-frequency operation by arranging the extension of an operation code outside the starting four bytes of an instruction format and assigning a code so that a machine can determine the accurate format of an instruction with only starting light bits of the code. SOLUTION: As for a base register 18, a multiplexer selector 19 directly controls a base multiplexer 20 and selects and sends a default base position to a CPR register file 15. A 2nd base register is gated from an instruction text to a B prime slot in the base register 18 in a 1st cycle and the multiplexer selector 19 is set to 1. A critical path, therefore, reaches a register for an address adder 16 from the base register 18 through the multiplexer 20 controlled by the selector 19 and the GPR register file 15. Thus, combination logic is excluded from the critical path.

公开(公告)号：JP2000099325A

公开(公告)日：2000-04-07

申请号：JP11055499

申请日：1999-04-19

Applicant: IBM

Inventor： MARK A CHECK ,  JOHN S RIPPUTAI ,  TIMOTHY J SLEEGEL ,  CHARLES F WEBB ,  MARK S FARRELL

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To provide a computer which has a millimode function for a system that has a central processor and also has operations of both normal mode and millimode. SOLUTION: This computer system having a millimode function gives the control to a millicode to continue a BHT(branch history table) operation excluding a case where a special situation occurs to need the control of an instruction fetch operation. A BHT 5 can be turned off to a certain section for execution of a code and cannot be disabled to all sections. A single free-running BHT functions to both normal mode and millimode used for a central processor that can be executed in a millimode by the BHT which indicates an instruction fetch containing both global BHT and millicode disabling functions.

公开(公告)号：JP2000029857A

公开(公告)日：2000-01-28

申请号：JP11471499

申请日：1999-04-22

Applicant: IBM

Inventor： CHARLES F WEBB ,  DEAN G BAYER ,  MARK S FARRELL ,  BARRY W CRAN ,  PARK KIN MAKU ,  JENNIFER A NAVARO

IPC: G06F15/177 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/52

Abstract: PROBLEM TO BE SOLVED: To provide a system serialization method by the early release of individual processors by generating a system standstill request and the request of the updating of a global resource by the processor, responding to the request and buffering the request in the processor during the processing. SOLUTION: Plural CPUs 210 and 211 in a system respectively execute an instruction from a simple instruction set and the instruction from a complicated instruction set in the execution controller 243 of hardware control. The respective CPUs 210 and 211 generate the system standstill request and the request of the updating of the global resource and respond to the request. Then, during the processing, the system standstill request and the request of the updating of the global resource are buffered in one or more of the CPUs 210 and 211. A system operation controller provided with a system serialization controller 220 or the like instructs the updating the global resource.

公开(公告)号：JP2000010942A

公开(公告)日：2000-01-14

申请号：JP11473199

申请日：1999-04-22

Applicant: IBM

Inventor： CHARLES F WEBB ,  DEAN G BAYER ,  MARK S FARRELL ,  BARRY W CRAN ,  PARK KIN MAKU ,  JENNIFER A NAVARO ,  TIMOTHY J SLEEGEL

IPC: G06F9/52 ,  G06F9/318 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To obtain a system which performs system serialization by early releasing of a processor by buffering a system standstill request and a request for updating on the processor. SOLUTION: Plural processors are included in this system and respective processors generates system standstill requests and requests to update global resources and responds to the requests. The system standstill request and the request for updating are buffered by one or plural processors. Then a system operation controller including a storage device controller SC 212 and a system serializing a controller 220 indicates the updating of the global resources. The global resources include an address conversion table entry and a protection key.

公开(公告)号：JP2000137610A

公开(公告)日：2000-05-16

申请号：JP9924299

申请日：1999-04-06

Applicant: IBM

Inventor： CHARLES F WEBB ,  JUDY SHAN SHAN CHEN JOHNSON

IPC: G06F9/38 ,  G06F9/22 ,  G06F9/28 ,  G06F9/30 ,  G06F9/302 ,  G06F9/305 ,  G06F9/308 ,  G06F9/318 ,  G06F9/32

Abstract: PROBLEM TO BE SOLVED: To reduce the number of millicode instructions and the number of machine cycles by permitting a millicode to supply a compilation function when a system is in a millimode millicode routine. SOLUTION: A cache memory unit 12 logically contains a writable inner code array 13 where a continuous address can be designated and millimode routines which are frequently called are stored in the inner code array 13. If the system enters a processor millimode, a millicode operating at a millimode state is supplied when the decoder of a processor decodes the routines and schedules them for execution. A millicode flag realizes special update and branch instruction, and the flag is cleared or is specially set for a millicode instruction. The millicode instruction for a compilation function processes one byte of an input pattern string and generates one byte of an output string, updates various pointers and state signs and prepares for a next byte processing in the string.

公开(公告)号：JP2000099330A

公开(公告)日：2000-04-07

申请号：JP11936799

申请日：1999-04-27

Applicant: IBM

Inventor： TIMOTHY J SLEEGAL ,  CHARLES F WEBB

IPC: G06F9/22 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48

Abstract: PROBLEM TO BE SOLVED: To prevent processors from being serial in most cases after the execution of STOSM or STNSM instruction and to attain improvement in performance by providing a termination interrupt logic for executing a specified instruction to change the system mask field of a program condition word without making it serial. SOLUTION: Parallelly with all the operation, the termination interrupt logic 11 continuously monitors and controls the execution completion of all the instructions and the write of the result. Besides, an asynchronous interruption logic 12 continuously monitors the presence/absence of asynchronous interruption under holding and when there is such interruption, it is presented to the termination interrupt logic 11. A PSW executing device 13 receives data to be loaded to a PSW from a fixed point executing device 7. This device 7 is provided with a logic for monitoring the change of a system mask bit. When the STOSM or STNSM instruction is under executing, this device 7 reports it to the termination interrupt logic 11 provided with an end counter.

公开(公告)号：JP2000029702A

公开(公告)日：2000-01-28

申请号：JP11948599

申请日：1999-04-27

Applicant: IBM

Inventor： TIMOTHY J SLEEGAL ,  CHARLES F WEBB

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To improve performance by avoiding unconditional processor serialization after the execution of an SPKA instruction by providing processor serializing control logic, which can execute a specific instructions without serializing processors in almost all cases. SOLUTION: This processor serialization control logic includes an extraction detecting logic mechanism which detects an fetching protection bit in a stored key being turned on as to an arbitrary instruction which was fetched recently, a SPKA execution detecting logic mechanism which detects a SPKA instruction having been executed recently, and a PSW executing device serializing control logic mechanism which serializes processors only, when both these events take place. A PSW executing device 13 receives data to be loaded to PSW from a fixed-point executing device 7. Once detecting the need to serialize the processors since the SPKA instruction was executed recently, the PSW executing device 13 notifies a report to end/interrupt logic 11, which actually starts the serializing process.

公开(公告)号：JP2000029685A

公开(公告)日：2000-01-28

申请号：JP11477199

申请日：1999-04-22

Applicant: IBM

Inventor： MARK A CHECK ,  RONALD M SMITH ,  JOHN S RIPTY ,  ERIK M SCHWARZ ,  TIMOTHY J SLEEGAL ,  CHARLES F WEBB

IPC: G06F9/355 ,  G06F9/30 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To enable a foating-point processor to determine the accurate format of an instruction by determining that an instruction is in 2nd format by decoding an operation code and gating information needed for address generation to an adder according to the decision result. SOLUTION: A 2nd base register is gated from an instruction text to a B prime slot in a base register 18 in a 1st cycle and a multiplexer selector 19 is set to 1. A critical path, therefore, reaches a register for an address adder 16 from the base register 18 through a multiplexer 20 controlled by the selector 19 and a GPR file 15. In this case, the floating-point processor decodes a 1st part of the operation code to determine that the instruction is in 2nd format, and gates information needed for address generation to the adder 16 according to the determination result.

公开(公告)号：JP2003216490A

公开(公告)日：2003-07-31

申请号：JP2002371417

申请日：2002-12-24

Applicant: IBM

Inventor： LIPTAY LYNNE M ,  MARK A CHECK ,  MARK S FARRELL ,  GIAMEI BRUCE C ,  CHARLES F WEBB

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F12/12

Abstract: PROBLEM TO BE SOLVED: To provide a method for ensuring that a line is present in an instruction cache by instructing a computing system. SOLUTION: In the method for ensuring that the line is present in the instruction cache by instructing the computing system, a line-touch instruction is selected, the line-touch instruction is recognized as one type of a branch instruction which does not branch, the line-touch instruction is executed to fetch a target line from a target address into the instruction cache, and execution of the line-touch instruction is interlocked by completion of the fetch of the target line for preventing execution of an instruction following the line-touch instruction until the target line reaches the cache. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2002116957A

公开(公告)日：2002-04-19

申请号：JP2001282710

申请日：2001-09-18

Applicant: IBM

Inventor： EARON SAY ,  CHANGU-RANGU KEVIN SHAMU ,  DEAN G BEAR ,  REBECCA S WIZNEUSKI ,  CHARLES F WEBB

IPC: G06F12/10

Abstract: PROBLEM TO BE SOLVED: To provide a mounting method of a support to a new real space control bit using an existing translation lookaside buffer mechanism in a microprocessor system. SOLUTION: In a processor system provided with the existing translation lookaside buffer mechanism, in order to support the real space control(RSC) bit which is a new processor control bit, a dedicated space bit which is an existing control bit in the translation lookaside buffer mechanism in re-defined as an ignore common segment bit and a new non-overlapping translation lookaside buffer mechanism entry is generated.