公开(公告)号：FR2410335A1

公开(公告)日：1979-06-22

申请号：FR7830979

申请日：1978-10-24

Applicant: IBM

Inventor： JEAN BRADFORD M ,  LANGSTON KEITH N ,  PARTRIDGE RICHARD L ,  SY KIAN-BON K

IPC: G06F12/08 ,  G06F12/10 ,  G11C8/00

Abstract: The disclosed embodiments filter out many unnecessary interrogations of the cache directories of processors in a multiprocessor (MP) system, thereby reducing the required size of the buffer invalidation address stack (BIAS) with each associated processor, and increasing the efficiency of each processor by allowing it to access its cache during the machine cycles which in prior MP's had been required for invalidation interrogation. Invalidation interrogation of each remote processor cache directory may be done when each channel or processor generates a store request to a shared main storage.