ROUTE SPECIFYING METHOD
    2.
    发明专利

    公开(公告)号:JPH05102977A

    公开(公告)日:1993-04-23

    申请号:JP16250391

    申请日:1991-06-07

    Applicant: IBM

    Inventor: SY KIAN-BON K

    Abstract: PURPOSE: To efficiently acquire path designation information between a start station and an object station in a multiplex loop network. CONSTITUTION: In the case of obtaining path designation information to send a frame from a start station connecting to a ring R1 to an object station connecting to a ring R3, the start station sends the frame and addresses of bridges B1, B2 or B4, B3 passed via each ring are written in a path designation information field of the frame and the obtained address information is used for succeeding frame transmission between the start station and the object station.

    ROUTING ARCHITECTURE FOR A MULTI-RING LOCAL AREA NETWORK

    公开(公告)号:CA1251839A

    公开(公告)日:1989-03-28

    申请号:CA478639

    申请日:1985-04-09

    Applicant: IBM

    Inventor: SY KIAN-BON K

    Abstract: ROUTING ARCHITECTURE FOR A MULTI-RING LOCAL AREA NETWORK The architecture provides a frame format and procedure for routing messages through a single ring or multi-ring communication system. Stations associated with the exchange of messages are located on the single ring or on different rings of the multi-ring communication system. The rings are connected by bridges to form a physical local area network. The frame format includes a plurality of control bits positioned within a Routing Information (RI) field, a frame control field and a frame status field. Messages are generated and structured in accordance with the frame format. A group of the control bits, in each message, is set with initial values according to the message type. Thus, different messages are characterized by a different sequence of control bit settings. A routing algorithm analyzes the message and depending on the status of the control bits, the message is processed and ultimately switched to its proper destination.

    COMBINED TERMINAL ADAPTER FOR SMDS AND FRAME RELAY HIGH SPEED DATA SERVICES

    公开(公告)号:CA2091084A1

    公开(公告)日:1993-09-11

    申请号:CA2091084

    申请日:1993-03-05

    Applicant: IBM

    Abstract: A terminal adapter interfaces between a Data Terminating Equipment (DTE) and either a Frame Relay (FR) or a Switched Multimegabit Data Service (SMDS) telecommunications network so that the type of network over which the DTE is communicating is transparent to the DTE. The TA performs mapping from one protocol to another so that a native FR DTE can access an SMDS network and so that a native SMDS DTE can access a FR network. The address mapping method performed by the TA uses a parallel table look-up technique which reduces the chance of collision (when two or more addresses hash into the same table entry), eliminates the traditional comparison function to detect a collision, and eliminates the traditional pointer technique when a collision occurs.

    7.
    发明专利
    未知

    公开(公告)号:DE69334011D1

    公开(公告)日:2006-05-24

    申请号:DE69334011

    申请日:1993-02-23

    Applicant: IBM

    Abstract: A terminal adapter interfaces between a Data Terminating Equipment (DTE) and either a Frame Relay (FR) or a Switched Multimegabit Data Service (SMDS) telecommunications network so that the type of network over which the DTE is communicating is transparent to the DTE. The TA performs mapping from one protocol to another so that a native FR DTE can access an SMDS network and so that a native SMDS DTE can access a FR network. The address mapping method performed by the TA uses a parallel table look-up technique which reduces the chance of collision (when two or more addresses hash into the same table entry), eliminates the traditional comparison function to detect a collision, and eliminates the traditional pointer technique when a collision occurs.

    COMBINED TERMINAL ADAPTER FOR SMD5 AND FRAME RELAY HIGH SPEED DATA SERVICES

    公开(公告)号:CA2091084C

    公开(公告)日:1998-05-12

    申请号:CA2091084

    申请日:1993-03-05

    Applicant: IBM

    Abstract: A terminal adapter interfaces between a Data Terminating Equipment (DTE) and either a Frame Relay (FR) or a Switched Multimegabit Data Service (SMDS) telecommunications network so that the type of network over which the DTE is communicating is transparent to the DTE. The TA performs mapping from one protocol to another so that a native FR DTE can access an SMDS network and so that a native SMDS DTE can access a FR network. The address mapping method performed by the TA uses a parallel table look-up technique which reduces the chance of collision (when two or more addresses hash into the same table entry), eliminates the traditional comparison function to detect a collision, and eliminates the traditional pointer technique when a collision occurs.

    ROUTING MECHANISM WITH ENCAPSULATED FCS FOR A MULTI- RING LOCAL AREA NETWORK

    公开(公告)号:CA1249866A

    公开(公告)日:1989-02-07

    申请号:CA478640

    申请日:1985-04-09

    Applicant: IBM

    Inventor: SY KIAN-BON K

    Abstract: ROUTING MECHANISM WITH ENCAPSULATED FCS FOR A MULTI RING LOCAL AREA NETWORK A method and apparatus for protecting the integrity of data in a multi-loop communication network is disclosed. A source station generates and forwards a frame with a unique format and a frame check sequence (FCS). At each bridge, an algorithm is provided to process the frame. If the frame is at a source bridge and not discarded, the FCS is preserved by encapsulating it in the Information field. The source bridge generates a new FCS, appends it to the frame and forwards the frame. Thereafter, each intermediate bridge generates its own FCS, appends it to the frame and forwards the frame. At the target bridge, no FCS is generated. The preserved FCS is forwarded as the FCS of the frame.

    10.
    发明专利
    未知

    公开(公告)号:FR2410335A1

    公开(公告)日:1979-06-22

    申请号:FR7830979

    申请日:1978-10-24

    Applicant: IBM

    Abstract: The disclosed embodiments filter out many unnecessary interrogations of the cache directories of processors in a multiprocessor (MP) system, thereby reducing the required size of the buffer invalidation address stack (BIAS) with each associated processor, and increasing the efficiency of each processor by allowing it to access its cache during the machine cycles which in prior MP's had been required for invalidation interrogation. Invalidation interrogation of each remote processor cache directory may be done when each channel or processor generates a store request to a shared main storage.

Patent Agency Ranking