公开(公告)号：DE2834964A1

公开(公告)日：1979-03-15

申请号：DE2834964

申请日：1978-08-10

Applicant: IBM

Inventor： BULA JOHN ,  PATRAWALA ASHOK CHAMPAKLAL

IPC: G11C11/41 ,  G11C11/413 ,  H03K5/151 ,  H03K19/096 ,  H03M7/00 ,  H03F3/16

Abstract: The prior art, low power ratioless true/complement driver is improved upon by connecting a first isolation FET (T2) so that its gate is connected to drain potential (VDD) and by connecting to the second isolation FET (T4) so that its gate is connected to the phase-splitting node (1). This enables the number of clock pulse sources necessary to operate the generator circuit to be reduced by one so that the speed of the generator circuit is increased, by virtue of the second isolation FET (T4) having a gate size substantially smaller than the gate size of the inverting FET (T3) so that it will more rapidly switch from its on-state to its off-state than does the inverting FET.