公开(公告)号：DE2834964A1

公开(公告)日：1979-03-15

申请号：DE2834964

申请日：1978-08-10

Applicant: IBM

Inventor： BULA JOHN ,  PATRAWALA ASHOK CHAMPAKLAL

IPC: G11C11/41 ,  G11C11/413 ,  H03K5/151 ,  H03K19/096 ,  H03M7/00 ,  H03F3/16

Abstract: The prior art, low power ratioless true/complement driver is improved upon by connecting a first isolation FET (T2) so that its gate is connected to drain potential (VDD) and by connecting to the second isolation FET (T4) so that its gate is connected to the phase-splitting node (1). This enables the number of clock pulse sources necessary to operate the generator circuit to be reduced by one so that the speed of the generator circuit is increased, by virtue of the second isolation FET (T4) having a gate size substantially smaller than the gate size of the inverting FET (T3) so that it will more rapidly switch from its on-state to its off-state than does the inverting FET.

公开(公告)号：IT1165312B

公开(公告)日：1987-04-22

申请号：IT2585279

申请日：1979-09-20

Applicant: IBM

Inventor： BERTIN CLAUDE L ,  BULA JOHN ,  MARTIN LARRY C ,  WILLIAMS THOMAS A

IPC: G11C17/12 ,  H01L23/525 ,  G11C17/00 ,  G11C

Abstract: Use of a residual charge bleed-off diode connected to the gate of an FET device in a Read Only Storage (ROS) is disclosed. The ROS is personalized by cutting selected gate leads in an array of FETs with a laser beam. Experience has shown that static electric charges on the lead due to handling prior to cutting become isolated at the gate after the gate lead is cut, producing an unpredictable conduction state for the FET instead of a solid off-state as desired. By providing a bleed-off diode which remains connected to the FET gate after the cut is made, the charges are allowed to leak away from those FETs whose gates have been cut while, at the same time, preventing the voltage of the FET gate from floating. The diode is oriented so as to offer a high impedance to current flowing from the gate node when the gate is biased for FET conduction. This minimizes the effect of the diode on circuit speed when the gate remains connected with the balance of the read only storage circuitry. If the gate and diode have been selectively severed from the balance of the read only storage circuitry, in the course of programming the storage, any residual charge on the gate is conducted through the diode by virtue of its reverse bias leakage or forward biased conduction state, depending upon the polarity of the residual charge on the gate.

公开(公告)号：DE2965440D1

公开(公告)日：1983-07-07

申请号：DE2965440

申请日：1979-08-23

Applicant: IBM

Inventor： BERTIN CLAUDE L ,  BULA JOHN ,  MARTIN LARRY C ,  WILLIAMS THOMAS A

IPC: G11C17/00 ,  G11C17/12 ,  H01L23/525

Abstract: Use of a residual charge bleed-off diode connected to the gate of an FET device in a Read Only Storage (ROS) is disclosed. The ROS is personalized by cutting selected gate leads in an array of FETs with a laser beam. Experience has shown that static electric charges on the lead due to handling prior to cutting become isolated at the gate after the gate lead is cut, producing an unpredictable conduction state for the FET instead of a solid off-state as desired. By providing a bleed-off diode which remains connected to the FET gate after the cut is made, the charges are allowed to leak away from those FETs whose gates have been cut while, at the same time, preventing the voltage of the FET gate from floating. The diode is oriented so as to offer a high impedance to current flowing from the gate node when the gate is biased for FET conduction. This minimizes the effect of the diode on circuit speed when the gate remains connected with the balance of the read only storage circuitry. If the gate and diode have been selectively severed from the balance of the read only storage circuitry, in the course of programming the storage, any residual charge on the gate is conducted through the diode by virtue of its reverse bias leakage or forward biased conduction state, depending upon the polarity of the residual charge on the gate.

公开(公告)号：IT7925852D0

公开(公告)日：1979-09-20

申请号：IT2585279

申请日：1979-09-20

Applicant: IBM

Inventor： BULA JOHN ,  BERTIN CLAUDE L ,  MARTIN LARRY C ,  WILLIAMS THOMAS A

IPC: G11C17/12 ,  G11C17/00 ,  H01L23/525 ,  G11C

Abstract: Use of a residual charge bleed-off diode connected to the gate of an FET device in a Read Only Storage (ROS) is disclosed. The ROS is personalized by cutting selected gate leads in an array of FETs with a laser beam. Experience has shown that static electric charges on the lead due to handling prior to cutting become isolated at the gate after the gate lead is cut, producing an unpredictable conduction state for the FET instead of a solid off-state as desired. By providing a bleed-off diode which remains connected to the FET gate after the cut is made, the charges are allowed to leak away from those FETs whose gates have been cut while, at the same time, preventing the voltage of the FET gate from floating. The diode is oriented so as to offer a high impedance to current flowing from the gate node when the gate is biased for FET conduction. This minimizes the effect of the diode on circuit speed when the gate remains connected with the balance of the read only storage circuitry. If the gate and diode have been selectively severed from the balance of the read only storage circuitry, in the course of programming the storage, any residual charge on the gate is conducted through the diode by virtue of its reverse bias leakage or forward biased conduction state, depending upon the polarity of the residual charge on the gate.

公开(公告)号：FR2402348A1

公开(公告)日：1979-03-30

申请号：FR7821336

申请日：1978-07-12

Applicant: IBM

Inventor： BULA JOHN ,  PATRAWALA ASHOK C

IPC: G11C11/413 ,  G11C11/41 ,  H03K5/151 ,  H03K19/096 ,  H03M7/00 ,  H03K3/353

Abstract: The prior art, low power ratioless true/complement driver is improved upon by connecting a first isolation FET (T2) so that its gate is connected to drain potential (VDD) and by connecting to the second isolation FET (T4) so that its gate is connected to the phase-splitting node (1). This enables the number of clock pulse sources necessary to operate the generator circuit to be reduced by one so that the speed of the generator circuit is increased, by virtue of the second isolation FET (T4) having a gate size substantially smaller than the gate size of the inverting FET (T3) so that it will more rapidly switch from its on-state to its off-state than does the inverting FET.

公开(公告)号：DE2825444A1

公开(公告)日：1979-01-04

申请号：DE2825444

申请日：1978-06-09

Applicant: IBM

Inventor： BULA JOHN ,  MARTIN LARRY C

IPC: H03K5/151 ,  H03K19/0185 ,  H03K19/096 ,  H03K5/156 ,  H03K19/08

Abstract: A high speed true/complement driver circuit is disclosed wherein the time interval between the address and memory select pulses are minimized by utilizing a high speed enhancement/depletion mode inverter pair followed by a clocked signal isolation stage. A pair of enhancement mode/depletion mode inverters connected in cascade configuration serves to generate the true and complement output signals which are isolated from noise at the input line by a symmetric pair of clocked FETs.