公开(公告)号：JP2001117770A

公开(公告)日：2001-04-27

申请号：JP2000304842

申请日：2000-10-04

Applicant: IBM

Inventor： MCDONALD ROBERT GREG ,  PEICHUN PETER RYUU ,  OLSON CHRISTOPHER HANS

IPC: G06F9/34 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To efficiently process plural out-of-order, speculative and optional updates for a register. SOLUTION: The register 200 includes at least one register bit and can include one or more sticky bits 201. An executing unit 204 is suitable for executing one set of computer instructions 202. A temporary result buffer 206 is constituted so as to receive register bit modification information provided by an instruction from the executing unit 204. The temporary result buffer 206 is suitable for storing the modification information in a pair of set /clear bits corresponding to individual register bits of the register. A committing function circuit is constituted so as to receive the pair of set/clear bits from the temporary result buffer 206 when the instruction is committed. The committing function circuit generates the updated bit in response to reception of the pair of set/clear bits.