公开(公告)号：DE3485201D1

公开(公告)日：1991-11-28

申请号：DE3485201

申请日：1984-06-28

Applicant: IBM

Inventor： BURSTEIN MICHAEL ,  HONG SE JUNE ,  PELAVIN RICHARD NEIL

IPC: H01L21/822 ,  G06F17/50 ,  H01L21/82 ,  H01L27/04 ,  H01L27/118 ,  H01L23/52

Abstract: For designing the layout of a master-slice VLSI chip steps for placing components and for determining the wiring pattern interconnecting them are alternated in an iterative process. The chip area is partitioned into subareas (G-, G + ) of decreasing size, the set of components is partitioned into subsets (X', X") which fit to the respective subareas, and after each partitioning step the global wiring is determined for the existing subnets of the whole network. Due to this interrelation of placement and wiring procedures, advantages with respect to total wire length, overflow number of wires, and processing time can be gained.