公开(公告)号：BR8801487A

公开(公告)日：1988-11-08

申请号：BR8801487

申请日：1988-03-30

Applicant: IBM

Inventor： BISCHOFF GARY ,  BLOKKUM DAG REIDAR ,  PENALOZA ANTONIO LEON III ,  PETERSON DAVID LAWRENCE

IPC: G06F12/14 ,  G06F12/02 ,  G06F12/00

Abstract: In a computer system, a plurality of processors or intelligent controllers separately utilize discrete pages of a large memory. Within each of these pages a processor can address a plurality of subdivisions or blocks utilizing the processors' address lines. Thus, separate processors having access to this memory and having a limited addressing capability can utilize a plurality of different pages of this memory, within an identical address range, and nevertheless remain confined to separate memory environments established for each of the separate processors. This is accomplished by use of a register system to point the separate processors to their assigned pages of the memory and a stored translate table to point to particular blocks of memory within the pages in accordance with a portion of an address generated by the processor accessing the memory. The register system is loaded at initialization of the computer system.