公开(公告)号：BR8801487A

公开(公告)日：1988-11-08

申请号：BR8801487

申请日：1988-03-30

Applicant: IBM

Inventor： BISCHOFF GARY ,  BLOKKUM DAG REIDAR ,  PENALOZA ANTONIO LEON III ,  PETERSON DAVID LAWRENCE

IPC: G06F12/14 ,  G06F12/02 ,  G06F12/00

Abstract: In a computer system, a plurality of processors or intelligent controllers separately utilize discrete pages of a large memory. Within each of these pages a processor can address a plurality of subdivisions or blocks utilizing the processors' address lines. Thus, separate processors having access to this memory and having a limited addressing capability can utilize a plurality of different pages of this memory, within an identical address range, and nevertheless remain confined to separate memory environments established for each of the separate processors. This is accomplished by use of a register system to point the separate processors to their assigned pages of the memory and a stored translate table to point to particular blocks of memory within the pages in accordance with a portion of an address generated by the processor accessing the memory. The register system is loaded at initialization of the computer system.

公开(公告)号：DE3850901D1

公开(公告)日：1994-09-08

申请号：DE3850901

申请日：1988-03-29

Applicant: IBM

Inventor： BLOKKUM DAG REIDAR ,  JOHNS CHARLES RAY ,  MOROZINK LEE JACK ,  PETERSON DAVID LAWRENCE

IPC: G06F12/06

Abstract: A system and method for contiguously addressing a memory system comprising a plurality of memory banks, each of which can have different capacity modules, or no module, plugged therein, comprises a matrix of logic cells. Each row of the cells receives a group of segment signal lines each indicating consecutively a fixed sized memory address segment. Each column receives a group of signals representing the capacity of memory modules currently in a corresponding memory bank. Taking the cell at row 1, column 1, if memory bank 1 contains the maximum capacity, then segment signals, when they appear on any of the four segment signal lines, pass through the column to form part of the memory addresses. If, however, memory bank 1 contains memory modules having an address range corresponding to, say, one segment, only the segment 1 line passes logically through the column. Except when the bank contains no memory, a bank 1 select signal (BS1) is generated. The second column of logic cells receives the first eight segment lines. If both banks 1 and 2 contain maximum capacity modules, then all eight segment lines pass through rows 1 and 2. If, however, bank 1 contains only one segment of memory, the memory cell 34 at row 1, column 2, picks up to three of the segment lines, depending on how many segments are in bank 2, and memory cell 32 at row 2, column 2 will pick the remaining segment line 5, if there are four segments in memory bank 2. In this way, the segment lines are picked consecutively, irrespective of the mix of modules in the memory banks.

公开(公告)号：DE3850901T2

公开(公告)日：1995-03-09

申请号：DE3850901

申请日：1988-03-29

Applicant: IBM

Inventor： BLOKKUM DAG REIDAR ,  JOHNS CHARLES RAY ,  MOROZINK LEE JACK ,  PETERSON DAVID LAWRENCE

IPC: G06F12/06

Abstract: A system and method for contiguously addressing a memory system comprising a plurality of memory banks, each of which can have different capacity modules, or no module, plugged therein, comprises a matrix of logic cells. Each row of the cells receives a group of segment signal lines each indicating consecutively a fixed sized memory address segment. Each column receives a group of signals representing the capacity of memory modules currently in a corresponding memory bank. Taking the cell at row 1, column 1, if memory bank 1 contains the maximum capacity, then segment signals, when they appear on any of the four segment signal lines, pass through the column to form part of the memory addresses. If, however, memory bank 1 contains memory modules having an address range corresponding to, say, one segment, only the segment 1 line passes logically through the column. Except when the bank contains no memory, a bank 1 select signal (BS1) is generated. The second column of logic cells receives the first eight segment lines. If both banks 1 and 2 contain maximum capacity modules, then all eight segment lines pass through rows 1 and 2. If, however, bank 1 contains only one segment of memory, the memory cell 34 at row 1, column 2, picks up to three of the segment lines, depending on how many segments are in bank 2, and memory cell 32 at row 2, column 2 will pick the remaining segment line 5, if there are four segments in memory bank 2. In this way, the segment lines are picked consecutively, irrespective of the mix of modules in the memory banks.

公开(公告)号：BR8801568A

公开(公告)日：1988-11-08

申请号：BR8801568

申请日：1988-04-04

Applicant: IBM

Inventor： BLOKKUM DAG REIDAR ,  JOHNS CHARLES RAY ,  MOROZINK LEE JACK ,  PETERSON DAVID LAWRENCE

IPC: G06F12/06 ,  G06F12/02

Abstract: A system and method for contiguously addressing a memory system comprising a plurality of memory banks, each of which can have different capacity modules, or no module, plugged therein, comprises a matrix of logic cells. Each row of the cells receives a group of segment signal lines each indicating consecutively a fixed sized memory address segment. Each column receives a group of signals representing the capacity of memory modules currently in a corresponding memory bank. Taking the cell at row 1, column 1, if memory bank 1 contains the maximum capacity, then segment signals, when they appear on any of the four segment signal lines, pass through the column to form part of the memory addresses. If, however, memory bank 1 contains memory modules having an address range corresponding to, say, one segment, only the segment 1 line passes logically through the column. Except when the bank contains no memory, a bank 1 select signal (BS1) is generated. The second column of logic cells receives the first eight segment lines. If both banks 1 and 2 contain maximum capacity modules, then all eight segment lines pass through rows 1 and 2. If, however, bank 1 contains only one segment of memory, the memory cell 34 at row 1, column 2, picks up to three of the segment lines, depending on how many segments are in bank 2, and memory cell 32 at row 2, column 2 will pick the remaining segment line 5, if there are four segments in memory bank 2. In this way, the segment lines are picked consecutively, irrespective of the mix of modules in the memory banks.

公开(公告)号：DE3885780T2

公开(公告)日：1994-05-19

申请号：DE3885780

申请日：1988-03-23

Applicant: IBM

Inventor： BISCHOFF GARY ,  BLOKKUM DAG REIDAR ,  PENALOZA III ANTONIO DELEON ,  PETERSON DAVID LAWRENCE

IPC: G06F12/14 ,  G06F12/02

Abstract: In a computer system, a plurality of processors or intelligent controllers separately utilize discrete pages of a large memory. Within each of these pages a processor can address a plurality of subdivisions or blocks utilizing the processors' address lines. Thus, separate processors having access to this memory and having a limited addressing capability can utilize a plurality of different pages of this memory, within an identical address range, and nevertheless remain confined to separate memory environments established for each of the separate processors. This is accomplished by use of a register system to point the separate processors to their assigned pages of the memory and a stored translate table to point to particular blocks of memory within the pages in accordance with a portion of an address generated by the processor accessing the memory. The register system is loaded at initialization of the computer system.

公开(公告)号：DE3885780D1

公开(公告)日：1994-01-05

申请号：DE3885780

申请日：1988-03-23

Applicant: IBM

Inventor： BISCHOFF GARY ,  BLOKKUM DAG REIDAR ,  PENALOZA III ANTONIO DELEON ,  PETERSON DAVID LAWRENCE

IPC: G06F12/14 ,  G06F12/02

Abstract: In a computer system, a plurality of processors or intelligent controllers separately utilize discrete pages of a large memory. Within each of these pages a processor can address a plurality of subdivisions or blocks utilizing the processors' address lines. Thus, separate processors having access to this memory and having a limited addressing capability can utilize a plurality of different pages of this memory, within an identical address range, and nevertheless remain confined to separate memory environments established for each of the separate processors. This is accomplished by use of a register system to point the separate processors to their assigned pages of the memory and a stored translate table to point to particular blocks of memory within the pages in accordance with a portion of an address generated by the processor accessing the memory. The register system is loaded at initialization of the computer system.