DEVICE WITH VERTICALLY ISOLATED SOURCE/DRAIN AND MANUFACTURING METHOD THEREOF

    公开(公告)号:JP2001274394A

    公开(公告)日:2001-10-05

    申请号:JP2001048699

    申请日:2001-02-23

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To provide a method for controlling dispersion of ion implantation and diffusion of dopant in an field effect transistor(FET) with a shallow junction that reduces a short-channel effect, and provide a device in this method. SOLUTION: The method includes a step for etching part of a polysilicon layer and exposing part of a gate dielectric 304; a step for forming a first oxide material 400 on the remaining polysilicon layer; a step for etching part of dielectric layer, exposing an isolation region 302, and forming a trench 500 in the substrate; a step for forming a second oxide layer 600 on the trench; a step for providing a spacer 700 adjoining to the first oxide layer and located on a part of the second oxide layer; a step for removing the exposing part of the second oxide layer and exposing a surface 800 of the trench; a step for removing the spacer 700; and a step for providing a semiconductor 1000 on the second oxide layer and the exposed surface of the trench.

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