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    2.
    发明专利
    未知

    公开(公告)号：DE951047C

    公开(公告)日：1956-10-18

    申请号：DEI0002150

    申请日：1950-09-26

    Applicant: IBM DEUTSCHLAND

    Inventor： DICKINSON ARTHUR HALSEY ,  PHELPS BYRON EUGENE ,  BERGFORS CARL ARTHUR

    IPC: G06F7/498 ,  G06F7/52

    Abstract: 656,139. Statistical apparatus. BRITISH TABULATING MACHINE CO., Ltd. Oct. 22, 1947, No. 28236. Convention date, Oct. 22, 1946. [Class 106 (i)] An electronic calculating machine settable to perform either multiplication or division by the repeating methods, has a divisor storage unit, a single accumulator for registering both the dividend and the quotient, each denomination of which comprises a group of trigger circuits operable by pulses, column shifting means controlling groups of pulse gating devices related to accumulator orders, and a source of operating pulses, and is characterized by means for applying repeatedly through the pulse gates to the accumulator numbers of pulses determined by the divisor so as to add repeatedly to the dividend value the complement of the divisor and " no go " detection means for determining when the addition no longer produces a carry from the highest denomination and terminating the complemental addition during the computing step when a carry is no longer produced. The trigger. The computing section comprises a large number of double-stability electronic trigger circuits. A typical trigger is shown in Fig. 3. In the OFF condition valve a is conducting and valve b is blocked. A negative pulse applied simultaneously to condensers 16a, 16b causes a reversal of this state : the lowering of voltage on the grid of valve a reduces its anode current and thus causes a positive pulse to be applied through a condenser 14a to the grid of valve b. As current starts to flow through valve b its anode voltage falls and so causes a further negative pulse to be applied through condenser 14b to the grid of valve b. Thus valve a becomes blocked and valve b conducting. This is known as the ON condition of the trigger. The next negative pulse to be applied to the condensers 16a, 16b will reverse the trigger again to its OFF condition. Positive pulses of similar magnitude do not produce this effect. The amount registers are built up from triggers, and each order is arranged to count ten input pulses to each output pulse. The circuit of the 5th order of the Dividend/ Product/Quotient Register is shown in Fig. 6j. It consists of four triggers designated 1, 2, 4 and 8 which, during the count, are in ON or OFF conditions according to the values they represent. Thus 6 is represented when trigger 1 is OFF, trigger 2 ON, trigger 4 ON and trigger 8 OFF. Each input pulse is applied simultaneously to both the grids in the first trigger and reverses it as described above. Each time trigger 1 is turned OFF a negative pulse from a tapping in the anode resistance of its valve a is passed to both grids of the next trigger 2 and also to the grid of valve b in trigger 8. When trigger 2 returns to OFF on the count of four a pulse passes to trigger 4 turning it ON, and so on up to the count of seven when triggers 1, 2 and 4 are all ON. The eighth input pulse causes these three triggers to be turned OFF in succession and a negative pulse from the anode resistance of valve a in trigger 4 passes to the grid of valve a only in trigger 8 switching this trigger to the ON position. The consequent rise in potential on the anode of the valve a is communicated to the grid of an extra valve X and causes this valve to start conducting. The ninth input pulse merely switches trigger 1 to the ON position to represent, with trigger 8, the count of nine. The tenth input pulse returns trigger 1 to OFF in the usual way but the effect of the consequent negative inpulse to trigger 2 is now counteracted by the lowered voltage on the anode of valve X which is applied to the anode of the a valve and the grid of the b valve in trigger 2. Thus, trigger 2 is not switched over in this case. However, the negative impulse from trigger 1 also passes along a wire 48 to the grid of valve b in trigger 8, switching OFF this trigger. Consequent upon this, the lowered voltage on the anode of valve a is transmitted to the grid of valve X causing this valve to cease conducting. Thus the circuit is returned to its initial state on receipt of the tenth input pulse, and a carry impulse passes along the " OUT " line. Entry of data. Cards are fed one by one and in an intermittent manner from a hopper P, Fig. 1, and past sensing brushes 17. The dividend and divisor (or multiplicand and multiplier), are represented in separate groups of card columns, Fig. 2, and the corresponding sensing brushes are connected by plugboard accordingly. As a card passes under the sensing brushes the occurrence of a data perforation causes a circuit to be completed through the usual cam and card lever contacts, plug connections, &c. to the appropriate plug socket PD, Fig. 6j, and causes a positive impulse at the grid of valve b of an entry control trigger such as N(5) (that associated with the fifth order being shown in detail). This causes the trigger to be switched ON, and the rise in potential on the grid of its valve b is communicated to the control grid of a pentode 97 which, however, does not conduct until the voltage on its suppressor grid is raised. Positive pulses for this purpose are supplied by cam contacts P2, P3, CB3, CB4 and P6, P7, CB1, CB2, Fig. 6d, which are operated in synchronism with the passage of the card data positions under the sensing brushes to switch a trigger B23 ON and then OFF again at each of the nine index points. Each time the trigger B23 is switched ON the drop in voltage at the anode of its valve b is communicated to the control grid of a valve B24 causing it to become momentarily non-conductive, thus giving rise to a positive pulse on line 101. These positive pulses are transmitted to all the entry control circuits, Fig. 6j &c. and to the suppressor grids of all the pentodes 97. They have no effect on the pentodes 97 until the potential on the control grid has been stepped up, as described above, upon sensing of a card perforation. Thereafter, each positive pulse causes the pentode concerned to conduct momentarily whereby the drop in potential in its anode circuit provides a negative input pulse for entry into the register. Thus each pentode 97 acts as a gate and allows negative pulses equal in number to the value of the digit sensed to pass to the counter. Entry of data into the other registers takes place in a similar manner. The computing stage. Initiation of the computing operations is by the closure of cam contacts between the " 11 " and " 12 " points in the machine cycle. This brings into operation a multivibrator which produces pulses at a frequency of approximately 50 kc,/s. Suitable circuits clip the output of the multivibrator and produce square-topped so-called " A " pulses and, 180 degrees out of phase with these, " B " pulses. These pulses are counted by a group of trigger circuits operating in binary fashion to give a scale of 16 count which forms the basis of the computing cycle. By means of further triggers and like devices, the equivalent of a commutator, supplying controlling voltages at pre-arranged periods in the computing cycle, is obtained. The arrangement and operation of the apparatus will be described with reference to the example set out in Fig. 8, i.e. the division of 99105 by 66. The dividend is entered in the first six orders of the accumulator DD-PQ, and the divisor in the first five orders of a register MC-DR, in the manner described above. The accumulator DD-PQ comprises twelve orders in all, and the quotient appears in orders 7 to 12 of this accumulator as a result of transfers from the lower orders during the process of division. Division is performed by repeatedly adding the complement of the divisor. When a " no go " condition occurs the last divisor subtraction is cancelled by adding the true divisor, the carry through, in this case, being suppressed ; after which column shift means operates to prepare for the next entry of the divisor complement moved one order to the right. If the divisor is equal to or less than the dividend or dividend remainder, then the addition of its complement produces a carry out of the highest order of the accumulator- DD-PQ signalling a " go " condition, and causes a " 1 " to be added in the appropriate order of the quotient section of the accumulator. The divisor is picked up from the register MC-DR by supplying ten pulses to the input of each denomination, pulses also going into the appropriate orders of the accumulator DD-PQ until blocked by output pulses from corresponding denominations of the register MC-DR. This gating is accomplished by pentode valves. A "go" condition in the accumulator DD-PQ is signalled by a transfer out of the highest denomination which prevents reversal of a trigger under the influence of the commutator circuit. In the absence of..this signal, reversal of the trigger occurs and conditions the read-out circuits to cause the true divisor to be entered into DD-PQ in the next cycle. The carry from the highest denomination is suppressed and the equivalent of a column shift takes place preparatory to the second stage of the division. Column shift is controlled by a group of triggers only one of which is in the " ON " condition at any particular stage. The ON state is passed on to the trigger after each " no go " condition and, by changing the conditions of a further group of pentodes the next reading from the register MC-DR is transmitted to the accumulator with the equivalent of a column shift. The apparatus continues to operate in this manner throughout six dividing stages. During the seventh stage " rounding off " of the last digit is performed. If the carries into the sixth order total 5 or more, then one unit is added into the seventh order. This rounding off is provided for by an initial entry of five pulses into the sixth order at the commencement of the seventh dividing step. The apparatus is set for multiplication by plugging the socket MPY to COM, Fig. 6d, whereby an electronic multiplier commutator

    3.
    发明专利
    未知

    公开(公告)号：DE2240433A1

    公开(公告)日：1973-03-08

    申请号：DE2240433

    申请日：1972-08-17

    Applicant: IBM

    Inventor： BEAUSOLEIL WILLIAM FRANCIS ,  PHELPS BYRON EUGENE

    IPC: G06F12/08 ,  G06F15/16 ,  G06F13/06

    Abstract: A hierarchical memory for a data processing system which is comprised of a number of different independent storage modules and a main memory backing store. Each data handling element of the system has an independent storage module associated with it as a dedicated buffer. A larger high speed main storage is used as a backing store. Each data handling element presumes that any data it needs is located in its dedicated buffer. If the data is not in the dedicated buffer, the data handling element scans all the other buffers until the desired data is located.

    4.
    发明专利
    未知

    公开(公告)号：DE898233C

    公开(公告)日：1953-11-30

    申请号：DEI0005319

    申请日：1951-12-19

    Applicant: IBM DEUTSCHLAND

    Inventor： PHELPS BYRON EUGENE

    IPC: G11B15/43 ,  G11B15/56 ,  H04L13/06

    Abstract: 697,276. Driving sound film or tape. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 14, 1951, No. 29334. Class 40 (ii) [Also in Group XVI] A tape feeding mechanism, particularly for magnetic tape, includes a driven supply spool 11, a driven take-up spool 27, a positive feed device 18, 19 therebetween, and means 30, 31, 32, 33 to direct one or more air jets against the surface of the tape 10 for taking up slack resulting from a disparity in the tape withdrawal rate and the tape feed rate. The spools 11, 27 are driven by spring belts 13, 29, respectively, which permit an element of slip, while the tape itself is driven positively by rollers 18, 19, geared together and driven through a non-slip belt 21 by a motor 20. Jets of air are pumped through ducts 32, 33 on to the tape 10 to form loops in slack parts and thus prevent the snatching and consequent breakage or other damage which may be caused by inertia effects such as when stopping and starting the drive.

    7.
    发明专利
    未知

    公开(公告)号：DE1111430B

    公开(公告)日：1961-07-20

    申请号：DEI0009980

    申请日：1955-03-21

    Applicant: IBM DEUTSCHLAND

    Inventor： ROCHESTER NATHANIEL ,  BASHE CHARLES JULIAN ,  BUCHHOLZ WERNER ,  CRAGO ROBERT PAUL ,  FOX PHILIP EVERETT ,  HADDAD JERRIER ABDO ,  PHELPS BYRON EUGENE

    IPC: G06F15/78

    Abstract: 800,505. Digital electric calculating-apparatus; electric digital-data-storage apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. March 18, 1955 [March 22, 1954], No. 7918/55. Class 106 (1). Electronic data processing apparatus includes input and output devices interconnected by a computer which employs variable length words, the lengths being demarcated by special coded characters. General. The electronic computer illustrated in Figs. 1a and 1b comprises a C.R.T. memory M, an accumulator including a C.R.T. store AS, and input/output magnetic tape units T. Words comprise a variable number of coded characters each represented by seven bits, Fig. 1c, comprising four numerical bits 1, 2, 4, 8, two zone bits A, B and a redundancy check bit C such as to make the total of " 1 "s in a character always odd. Numbers are in decimal form and have their digits represented in the excess-three code, the zone bits being "0." Words are separated by field marks " +," "-," Fig. 1c, the mark " - " being used only for numbers stored in the memory to indicate a negative sign. In the accumulator store, a negative sign is indicated by numerical " 9 " with " + " field mark zone digits. The field marks and other special characters are detected by recognition circuits CRC associated with two characters registers CR1, CR2, Fig. 1b, which receive characters as they are read out from the memory or accumulator store via main bus MB or accumulator storage bus AB, and also form a buffer between the memory and the tape units. The memory comprises 50 pairs of C.R.T.s; a pair is selected by unit selector US and a " left " or " right " C.R.T. of this pair by memory left/right control MC. The beam in the selected C.R.T. may be deflected to one of 100 character positions by memory deflection circuits MD. The circuits US, MC, MD are controlled by the portions indicated of a 4-decimal-digit address through memory switch MS. A word location is given by the address of the "right-hand " field mark (the one with the higher address number); e.g. the address of the number 123, 456, Fig. 1h, is 0037. Transfer to and from tape (writing and reading) is effected in the order of increasing address numbers (" left to right "), but transfer between the memory and the accumulator is effected in the reverse order (" right to left "). The accumulator store AS, which normally stores one word only, comprises a single C.R.T. having 100 character positions selected by deflection circuits ASD controlled by 2-digit addresses through switch ASS, addresses normally being selected in ascending order. A separate computer cycle is provided for dealing with each character, timing control signals being obtained from clock C and waveform generator WG. An instruction word, e.g. the word at address 0008, Fig. 1h, always comprises 6 characters, viz., an operation-defining character, an " address " portion (4 characters or digits) and a field mark, and is read out from the memory in ascending address order (operation character first). The addresses are sequentially set up in a programme counter PC (in a 1, 2, 2, 4 code) during the 6 successive character cycles of " instruction time," the computer being controlled by instruction timer IT to pass the operation character to interpreter II and the address digits via memory address translator MAT to a register MAR operating in the 1, 2, 2, 4 code. At the commencement of the subsequent " execution time," in which a timer ET is selected to carry out the instruction, the address in register MAR is transferred to counter MAC and normally applied via code ambiguity eliminator MAE to the switch MS to select a required memory location, and the amount registered on a two-decimal-digit starting point counter SPC may be transposed to an accumulator storage address counter AAC and applied via ambiguity eliminator ASAE to switch ASS to select an accumulator location when required. During subsequent execution character cycles, the count in MAC may be stepped down and the count in AAC stepped up to select successive character positions in the memory and accumulator store. Words from M and AS may be sent character by character to the comparator adder time/complement circuits CATC to perform arithmetic and other operations. The flow of information is controlled by routing circuits R. During a portion of each character cycle a regeneration counter RC is effective systematically to regenerate all the stored bits in the C.R.T.s, 50 tubes (one in each pair) being regenerated simultaneously in the main memory M. In some instructions, the memory is not used, and the " address " number in MAC is employed, e.g. to determine how the word stored in AS is to be modified, or to select, through in/out unit selector IOS, one of the tape or other input/ output units. The character emitter CE emits timed pulses representing certain numeral and other characters. The electronic circuits consist primarily of Eccles-Jordan double triode trigger circuits (T), coincidence switches (S) which usually produce a negative output in response to two positive inputs, diode AND and OR circuits, inverters (I) and cathode followers (CF); circuit diagrams for these components are given in the Specification. The computer is described below under the following headings: (1) Clock and waveform generator; timing signal rotation. (2) Basic counter. (3) Ambiguity eliminator. (4) Input/Output. (5) Character Registers and Character Recognition Circuits. (6) Memory address translator and register. (7) Memory address counter and ambiguity eliminator. (8) Programme counter. (9) Regeneration counter. (10) Memory and associated selection circuits. (11) Accumulator storage and associated circuits. (12) Memory and accumulator sign circuits. (13) Comparator, adder, true complement and associated circuits. (14) Adder and complementer. (15) Instruction timer; sequence of events during instruction time. (16) Instruction interpreter. (17) Routing circuits. (18) Execution timers; instructions. (19) Add or subtract instruction. (20) Reset add and subtract instructions. (21) Add to memory instruction. (22) Compare instruction. (23) Multiplication. (24) Division. (25) Instructions involving accumulator, store but not memory, rounding off; positioning decimal point. (26) " Store "-instruction. (27) Transfer of control instructions. (28) Tape instructions. (1) Clock and waveform generator; timing signal notation. The clock C, Fig. 1b, comprises a 1 mc/s. oscillator and a pulse distributing circuit similar to that of Specification 750,259 for defining regeneration (G), and read (R) and write (W) periods in a character cycle. The computer may be held in the " G " portion of the cycle under control of a " repeat regeneration" signal. The clock controls waveform generator circuits WG which develop timing signals such as those shown in Figs. 2c and 2i. Signals are denoted by the number of microseconds their leading edges occur after an index time G0-W7 and by their duration (D); e.g. the pulse L202, Fig. 2i, would be denoted WO1 (D2) meaning a pulse starting 1 Ás. after W0 and lasting 2 Ás. A train of pulses may also be denoted; e.g. R22 (D1)4 indicates 4 pulses each of 1 Ás. duration and starting 2 Ás. after R2 and succeeding index times (L203, Fig. 21). An inverted or complementary signal is indicated by c; e.g. L124c is a positive pulse coinciding with L124, Fig. 2c. (2) Basic counter. A decimal counting circuit CT1, Fig. 1d, comprises four double-triode triggers 101, 102, 103, 104 having weighted values 1, 2 (called 2C), 2, 4 respectively. The triggers may be reset to the " off " or " O " condition (right triode conducting) by a positive pulse at 11, inverted in 131 and applied through diodes 133-136 to the right anodes. Trigger 101 responds to negative input pulses at 15 and, for every second pulse, supplies a negative output pulse to diodes 105 and 107 connected respectively via line 107a to the right-hand input only of trigger 102 and via diode 110 and line 112 to both inputs of 103. Thus, after the second input pulse, trigger 102 is switched " on " and applies a positive gating potential via resistor 108 to diode 107 to allow subsequent pulses from 101 to switch trigger 103. Triggers 101, 103, 104 then operate in normal binary fashion until trigger 104 is switched back to " O " in response to the tenth input pulse, when the negative pulse from its right anode is applied via diode 116 to carry output terminal 27, and to line 118 to reset trigger 102. A value may be entered also in parallel, during a " dumping " operation, by selectively applying "1"-representing negative pulses to terminals 16-19. The registered value may be changed to its 9's complement by a negative pulse applied via 13 to line 126 to switch all the - triggers to the opposite condition, the connections between the triggers being inhibited by applying a positive signal at 12 to inverter 121 so as to drive line 122 negative. Output terminals 21-26 enable the registered value to be read out. After the complementing, and possibly after parallel entry, the representation of any value between 2 and 7 will be different from that obtained during normal stepping of the counter. This alternative representation is translated into the normal one in an ambiguity eliminator (described below). A simplified counter CT2 (Fig. 1e, not shown) having no provision for complementing, also is employed. (3) Ambiguity eliminator. The circuit AE, Fig. 1f, is a code interpreting circuit which receives respectively from terminals 21, 23-26 of a counter such as CT1, Fig. 1d, a negative input at 16 when the " 1 " trigger is " on," positive inputs at 17, 18 when the " 2 " triggers (102 and 103 respectively) are " on," and a positive input at 19 or 20 according to whether the "4" trigger is " off " or " on," and supplies positive outputs selectively to 21-24, corresponding to the weighted values 1, 2G, 2, 4, to represen

    8.
    发明专利
    未知

    公开(公告)号：DE1019489B

    公开(公告)日：1957-11-14

    申请号：DEI0002115

    申请日：1950-09-23

    Applicant: IBM DEUTSCHLAND

    Inventor： HOOD JAMES DE KALB ,  PHELPS BYRON EUGENE

    IPC: G06F7/02

    Abstract: 614,016. Statistical apparatus. BRITISH TABULATING MACHINE CO., Ltd. June 28, 1946, No. 19420. Convention date, June 30, 1945. [Class 106 (i)] A record card collating machine for collating cards having in each column intrazone index positions which represent numbers (1 to 9), and zone index positions (R, X, O) which, in combination with the intrazone index positions, represent other characters (letters or the alphabet &c.), one at least of the zone index positions being a dual zone index position in representing a character when alone in a column, is characterised by means to sense a pair of record cards, storage relays operated under control of the sensing means according to marked zone and intrazone index positions on the pair of cards, a network of relay contacts controlled by the storage relays and adapted to close one ot two circuits according to whether the sensed index positions on one card of the pair represents a character which is greater than or less than that represented by the sensed index positions on the other card, according to a predetermined scale of values and excepting the condition when a dual zone index position is on both cards, but is in combination with an intrazone position on only one card of the pair, a second network of relay contacts adapted, when the excepted condition occurs, to close the circuit of a correction relay of which the contacts are adapted, when the correction relay is energized, to alter the circuit closed by the first network. The invention is applied to a collating machine of the type described in Specifications 523,652, 523,709 and 523,710, the general arrangement of which is shown in Fig. 1. Cards from a hopper PH are fed in the usual way past a first set of sensing brushes QB termed the " sequence station," and then past a second set of brushes PB termed the " primary station." This enables a comparison to be made between control data on any " primary " card and similar data on the following " primary " card. The reading at the " primary station is also compared with the reading from a secondary " card, fed from a hopper SH, at the " secondary station " sensing brushes SB. As a result of these comparisons, one or the other of the clutch magnets (not shown) controlling the drives of the primary and secondary feeding means respectively, are energized, and further magnets PRM, SRM1, &c. control deflecting blades 306, 307, 308 to direct the cards into appropriate pockets 1, 2, 3, 4. According to the present invention, the control data on the cards may be numerical, alphabetical, or a mixture of both (e.g. " EX38D3-13 "), the code being shown in Fig. 4. The (ascending) order of magnitude adopted is as follows: Blank column, the - symbol (R perforation), letters A to Z, numbers 0 to 9. The three card sensing stations SB, PB, QB are shown diagrammatically in Fig. 3a, the plugboards being indicated at points SJ, PJ, QJ, SJJ, &c. The sensing of perforations at e.g. the secondary station causes the setting up of relays IS ... XRS of a " secondary group " through the medium of a valve VS. Contacts 741a ... XRa are respectively closed at prearranged times in the machine cycle by relays 741 ... XR, Fig. 3c. Relay 741 is energized at the " 7," " 4 " and " 1 " times in the cycle, and similarly with the other relays, under the control of cam-operated contacts CR21 ... 26, the closing of a contact raising the potential on the grid G1 of an associated valve sufficiently to allow anode current to flow and energize the relay. Where a hole is sensed in a card, current flows, e.g. from a reading brush SB, Fig. 3a, to a valve VS, and anode current then flows to the pick-up coils P of one or more of the relays IS ... XRS whose circuits have been closed by the relays 741 ... XR, Fig. 3c. Holding circuits are established by the coils H of relays IS ... XRS, &c., and also contacts are transferred in a comparing network, Fig. 3e, so that when a circuit is completed, subsequently, through this network, one of three wires P" lo," S" lo," and E" out " is energized according to whether the control data on the primary card is lower, higher, or equal to that on the secondary card. A similar comparing network, Fig. 3d, is used between the primary and sequence stations, but the relays HEQ and HEP take the place of relays 1S . . . 6S and 1P ... 6P in the network. Three thyratrons V91, V92, V93, Fig. 3a, are operated from the sensing brushes PB, QB in such a manner that, when the readings are equal, both V92 and V93 fire, causing energization of relays HEP and HEQ, but if V92 fires earlier, the relay HEQ opens contacts HEQb preventing subsequent firing of V93, or if V93 fires earlier, contacts HEPb are transferred causing V91 to be fired subsequently instead of V92. Supplementing the other relays, correction means are required to provide for the cases where a blank occurs in one compared column and an O or a dash symbol, or any alphabetic character whose designation includes an O hole, appears in the other compared column; also where an O occurs in one compared column and any alphabetic character whose designation includes an O appears in the compared column. These means comprise relays SBR and PBR, Fig. 3e, in the case of the primary and secondary comparing circuit, and relays PQZ and QBZ in the case of the primary sequence circuit, Fig. 3d. Three chains of contacts LQb, HEQb . . . , 1Pb, 2Pb . . . , 1Sb, 2Sb . . . control the energization of the relays SBR, PBR, PQZ, QBZ. According to the results from the comparing circuits, a relay PL, PES or SL, Fig. 3e, and a relay QH, QE or QL, Fig. 3d, are energized and control the delivery of cards to appropriate pockets in accordance with the plugboard arrangements for the results desired. In a modification, the valves V58, Fig. 3c, are replaced by thyratrons (Fig. 3g, not shown) which obviate the need for the relays 741 . . . XR and their holding circuits, the relays 1S . . . XRS, &c., being simply included in the anode circuits of the thyratrons.

    9.
    发明专利
    未知

    公开(公告)号：DE950858C

    公开(公告)日：1956-10-18

    申请号：DEI0006768

    申请日：1952-12-28

    Applicant: IBM DEUTSCHLAND

    Inventor： PHELPS BYRON EUGENE

    IPC: G06K7/08 ,  G11B5/00 ,  G11B5/008 ,  G11B5/02 ,  H04N5/782

    Abstract: 748,996 Magnetic recording and reproducing heads. INTERNATIONAL BUSINESS MACHINES CORPORATION. Aug. 21, 1952 [Dec. 31, 1951], No. 21006/52. Class 40(2) [Also in Group XIX] Successive electrical pulses are recorded on a moving magnetic medium (e.g. a wire or tape, not shown) by applying alternate pulses to opposing windings 15a, 15b of a recording head 15 whereby each pulse is recorded by subjecting the medium to a flux in a changed direction. In the recording apparatus, the windings are energized by electron discharge means under control of a bistable electric trigger. As shown in Fig. 4, pulses to be recorded are applied at terminal IN to the bistable trigger pair V5, V6 the anode outputs of which are taken via lines 9, 10, directly and through inverter V9 respectively, to the control grids of pentode drivers V10, V11 connected to the windings 15a, 15b. Either V10 or V11 is conducting so that magnetic flux is generated continually, in one direction or the other according to the condition of the trigger which is switched over by each input pulse. To prevent recording, a relatively positive potential is applied to line 12 which causes inverters V7, V8 to conduct to apply permanent negative potentials to the control grids of both V10 and V11, and to set the trigger pair in the starting condition with V6 conducting. When a binary representation, e.g. "yes" and "no," is to be recorded, two separate tracks are used. The reading' circuit, Fig. 5, comprises opposed windings 16a, 16b connected to triodes V1, V2 arranged to feed in pushpull two pentodes V3, V4 having a common return anode circuit including a relay RL-1. Thus the relay will be energized by change of flux in either direction sensed by reading head 16.

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