公开(公告)号：CA1005884A

公开(公告)日：1977-02-22

申请号：CA144643

申请日：1972-06-14

Applicant: IBM

Inventor： KENDALL FRANK T ,  PIERCE DONALD L ,  WEIKEL WALTER J

IPC: G06K13/077

Abstract: A high precision high speed bidirectional step motor assembly, without gears or commutation, rapidly and precisely positions standard 80 column record cards without oscillation relative to a combined reading, punching and printing station of a card data recorder. Read cells and punch-print elements are separated by 2 units of card column displacement (2 x 0.087 inches). Four step drive excitation for the step motor (three drive pulses and one "hold" or "detent" pulse) is derived from pre-existing recorder circuits associated with buffer storage and logic sections. This permits reading, punching and printing operations to occur in synchronization with buffer and logic operations while card motion is definitely stopped in the holding stage of the motor drive cycle. A pressure roller which engages the card with a feed wheel extension of the step motor is disengaged either manually or by operation of conventional registration mechanisms as the cards are fed to the initial registration position of the combined station (card column "0" under punch and print elements; column 2 under read cells). In read mode the first dummy cycle of step motor excitation backs up the card one column returning column 1 of the card to the read position. The advantage of this is that the read cells can be utilized in a dual mode to detect the leading edges of cards as a condition of the registration operation and to read card apertures. In punching-printing mode the usual first "dummy" cycle of forward stepping is taken.

公开(公告)号：CA1168370A

公开(公告)日：1984-05-29

申请号：CA387659

申请日：1981-10-09

Applicant: IBM

Inventor： HENDRICKSON THOMAS A ,  MACAULEY GEORGE C ,  PIERCE DONALD L ,  ROEFER ROBERT W ,  STRICKLAND ALAN B

IPC: G06F9/22 ,  G06F3/02 ,  G06F3/023 ,  G06F3/048 ,  G06F9/06 ,  G06F9/26 ,  G06F13/10 ,  G06F15/00 ,  H03M11/04 ,  H03M11/22 ,  G06F15/02 ,  G06F9/34

Abstract: CT9-80-006 An improved peripheral processor architecture wherein the function controlling information of a program is separated from portions of the sequence of execution controlling information and each are stored in the form of tables. The function controlling information takes the form of a table including a plurality of function specifying entries. The function execution sequence controlling information takes the form of a table of pointers. In this invention, function controlling entries, each having a plurality of fields for defining, modifying, and specifying the functions and related data to be executed, need not be repetitively duplicated throughout the program. Instead, the shorter pointers to the function table entries can be provided in the sequence table in the sequence in which the functions are to be executed. In a keyboard display controller application, further economy of storage is obtained by retaining a first level of function specifying information in the sequence table in the form of a bit identifying whether the function to be executed is a complex function, in which case the pointer identifies an entry in the function control statement table, or whether the function to be executed is merely the display of information on the display, in which case the pointer in the sequence table entry specifies an entry in a guidance table.

公开(公告)号：CA969667A

公开(公告)日：1975-06-17

申请号：CA155042

申请日：1972-10-26

Applicant: IBM

Inventor： BATTISTONI RICHARD B ,  LETTIERI JOHN ,  PIERCE DONALD L ,  WEIKEL WALTER J

IPC: G06K1/04 ,  G06K1/06 ,  G06K5/00