公开(公告)号：US3735362A

公开(公告)日：1973-05-22

申请号：US3735362D

申请日：1971-09-22

Applicant: IBM

Inventor： ASHANY R ,  AUDRETSCH L ,  PISTERZI M

IPC: G06F13/42 ,  H04L12/46 ,  G06F13/00

CPC classification number: G06F13/4213 ,  H04L12/4637

Abstract: Units of a data processing system communicate on a ring connection of shift register stages. The number of stages in a shift register is made small to avoid the delays that accompany the long data paths of a large ring system. Interconnecting stages are provided to direct a message on a first ring to a second ring according to an address contained in the message. Several useful configurations are disclosed. With this arrangement, a system of small rings can be expanded without correspondingly lengthening the average time for transmitting a message in the system.

Abstract translation: 数据处理系统的单元在移位寄存器级的环形连接上进行通信。 移位寄存器中的级数很小，以避免伴随大环系统的长数据路径的延迟。 提供互连级以根据消息中包含的地址将第一环上的消息引导到第二环。 公开了几种有用的构造。 利用这种布置，可以扩展小环的系统，而不会相应地延长在系统中传送消息的平均时间。