公开(公告)号：US3859637A

公开(公告)日：1975-01-07

申请号：US37461673

申请日：1973-06-28

Applicant: IBM

Inventor： PLATT STEVEN ,  POMERANZ JEHOSHUA N ,  TEWARSON DINESH K

IPC: G11C5/00 ,  G11C8/18 ,  G11C11/34 ,  G11C11/415 ,  G11C11/417 ,  G11C11/418 ,  H03M7/00 ,  G11C11/40

CPC classification number: G11C11/418 ,  G11C5/00 ,  G11C8/18 ,  G11C11/415 ,  G11C11/417 ,  H03M7/00

Abstract: A monolithic semiconductor array of bi-level powered memory cells is provided with a number of on-chip row and column primary latching circuits. The primary latching circuits allow for the down-powering of the on-chip row and column address decoders after a particular chip and a particular storage cell on the chip have been selected by a respective address signal and a set signal. An auxiliary latching circuit, substantially identical to each of the aforesaid primary latching circuits, also is provided on-chip and receives the same set signal as does each primary latching circuit. The primary latching circuits and the auxiliary latching circuit are ''''set'''' substantially simultaneously by the set signal. The setting of the auxiliary latching circuit initiates a signal which downpowers each of the on-chip address decoders. Means are also provided on-chip for resetting each of the selected primary and the auxiliary latching circuits upon the termination of the chip select signal.

Abstract translation: 双层电源存储单元的单片半导体阵列具有多个片上行和列主要锁存电路。 主要锁存电路允许在芯片上的特定芯片和芯片上的特定存储单元被相应的地址信号和设置信号选择之后片上行和列地址解码器的下电。 基本上与上述主锁存电路基本相同的辅助锁存电路也被提供在片上并且接收与每个主锁存电路相同的设置信号。 主锁存电路和辅助锁存电路通过设定信号基本上同时设定。 辅助锁存电路的设置启动一个使每个片上地址解码器下降的信号。 在芯片选择信号终止时，芯片还提供用于复位所选择的主要和辅助锁存电路中的每一个的装置。

公开(公告)号：DE2329643A1

公开(公告)日：1974-01-24

申请号：DE2329643

申请日：1973-06-09

Applicant: IBM

Inventor： PLATT STEVEN ,  POMERANZ JEHOSHUA NAPHTALI ,  TEWARSON DINESH KUMAR

IPC: H03F3/45 ,  H03K5/003 ,  H03K19/018 ,  H03K19/082 ,  H03K5/00

Abstract: A signal voltage level translating circuit receives an input electrical signal having predetermined voltage swings about a first predetermined voltage level and translates the voltage level of the signal so that at the output there is provided an output electrical signal having the same voltage swings about a second predetermined voltage level translated with respect to the first voltage level. An input transistor has its base connected to the input node and its emitter connected to one end of a first impedance element having its other end connected to the collector of a current source transistor. A fixed reference voltage is applied to the base of a reference voltage transistor having its emitter connected to one end of a second impedance element having an impedance equal to that of the first impedance element. The other end of the second impedance element is connected to the collector of a diode-connected transistor having its base connected to the base of the current source transistor. The emitter of the diode-connected transistor is connected to the emitter of the current source transistor. If implemented in the form of a monolithic integrated circuit, the diode-connected transistor and current source transistor may have the same base and the same emitter. The translated signal is taken at the output where the first impedance element is connected to the collector of the current source transistor.

公开(公告)号：CA1023857A

公开(公告)日：1978-01-03

申请号：CA169272

申请日：1973-04-13

Applicant: IBM

Inventor： PLATT STEVEN ,  POMERANZ JEHOSHUA N

IPC: G11C11/414 ,  G11C8/16 ,  G11C11/411 ,  G11C7/00

Abstract: An array of memory cells is provided with each cell having a word top line, a word bottom line and a pair of bit lines connected thereto. Either a standby voltage or a select voltage is applied to each of the lines, whereby any cell of the array may be selected by applying a select voltage to the two word lines and one or both bit lines connected to the cell. In one of the disclosed embodiments, the cells are arranged in columns and in groups of rows. Each of a plurality of word top drive lines is connected to all of the rows of the cells of a respective group to select any group of rows, each of a plurality of word bottom drive lines is connected to a respective row of cells in each of the groups to select one row of the selected group, and a plurality of pairs of bit lines are provided with each pair connected to the cells of a respective column to select one column and thereby one cell of the selected row. Each cell preferably comprises a cross-coupled pair of transistors each having a collector and first and second emitters. The word top lines are connected to the collector load impedances, the word bottom lines are connected to the first emitters, and the bit lines are connected to the second emitters.

公开(公告)号：CA1014623A

公开(公告)日：1977-07-26

申请号：CA174372

申请日：1973-06-19

Applicant: IBM

Inventor： PLATT STEVEN ,  POMERANZ JEHOSHUA N ,  TEWARSON DINESH K

IPC: H03F3/45 ,  H03K5/003 ,  H03K19/018 ,  H03K19/082

Abstract: A signal voltage level translating circuit receives an input electrical signal having predetermined voltage swings about a first predetermined voltage level and translates the voltage level of the signal so that at the output there is provided an output electrical signal having the same voltage swings about a second predetermined voltage level translated with respect to the first voltage level. An input transistor has its base connected to the input node and its emitter connected to one end of a first impedance element having its other end connected to the collector of a current source transistor. A fixed reference voltage is applied to the base of a reference voltage transistor having its emitter connected to one end of a second impedance element having an impedance equal to that of the first impedance element. The other end of the second impedance element is connected to the collector of a diode-connected transistor having its base connected to the base of the current source transistor. The emitter of the diode-connected transistor is connected to the emitter of the current source transistor. If implemented in the form of a monolithic integrated circuit, the diode-connected transistor and current source transistor may have the same base and the same emitter. The translated signal is taken at the output where the first impedance element is connected to the collector of the current source transistor.

公开(公告)号：DE2306866A1

公开(公告)日：1973-11-15

申请号：DE2306866

申请日：1973-02-13

Applicant: IBM

Inventor： PLATT STEVEN ,  POMERANZ JEHOSHUA NAPHTALI

IPC: G11C11/414 ,  G11C8/16 ,  G11C11/411 ,  G11C7/00

Abstract: An array of memory cells is provided with each cell having a word top line, a word bottom line and a pair of bit lines connected thereto. Either a standby voltage or a select voltage is applied to each of the lines, whereby any cell of the array may be selected by applying a select voltage to the two word lines and one or both bit lines connected to the cell. In one of the disclosed embodiments, the cells are arranged in columns and in groups of rows. Each of a plurality of word top drive lines is connected to all of the rows of the cells of a respective group to select any group of rows, each of a plurality of word bottom drive lines is connected to a respective row of cells in each of the groups to select one row of the selected group, and a plurality of pairs of bit lines are provided with each pair connected to the cells of a respective column to select one column and thereby one cell of the selected row. Each cell preferably comprises a cross-coupled pair of transistors each having a collector and first and second emitters. The word top lines are connected to the collector load impedances, the word bottom lines are connected to the first emitters, and the bit lines are connected to the second emitters.