公开(公告)号：US3927371A

公开(公告)日：1975-12-16

申请号：US44328474

申请日：1974-02-19

Applicant: IBM

Inventor： POMERANZ JEHOSHUA NAPHTALI ,  SCHNURMANN HENRI DANIEL

IPC: G01R31/319 ,  G06F11/26 ,  G01R15/12 ,  G01R31/30 ,  G06F11/00

CPC classification number: G01R31/31919 ,  G06F11/261

Abstract: A system for testing large scale integrated circuits. The circuitry in an integrated package such as a card, module or a semiconductor chip is viewed as a partially functional logic unit. This circuitry is complemented with off-package logic to allow the combination to act as a complete functional logic unit to which functional test patterns may be applied. The complementary logic is preferably simulated in the memory of a computer-controlled tester.

Abstract translation: 一种用于测试大规模集成电路的系统。 诸如卡，模块或半导体芯片的集成封装中的电路被视为部分功能逻辑单元。 该电路补充了非封装逻辑，以允许组合作为可应用功能测试模式的完整功能逻辑单元。 互补逻辑优选地在计算机控制的测试器的存储器中被模拟。

公开(公告)号：DE2306866A1

公开(公告)日：1973-11-15

申请号：DE2306866

申请日：1973-02-13

Applicant: IBM

Inventor： PLATT STEVEN ,  POMERANZ JEHOSHUA NAPHTALI

IPC: G11C11/414 ,  G11C8/16 ,  G11C11/411 ,  G11C7/00

Abstract: An array of memory cells is provided with each cell having a word top line, a word bottom line and a pair of bit lines connected thereto. Either a standby voltage or a select voltage is applied to each of the lines, whereby any cell of the array may be selected by applying a select voltage to the two word lines and one or both bit lines connected to the cell. In one of the disclosed embodiments, the cells are arranged in columns and in groups of rows. Each of a plurality of word top drive lines is connected to all of the rows of the cells of a respective group to select any group of rows, each of a plurality of word bottom drive lines is connected to a respective row of cells in each of the groups to select one row of the selected group, and a plurality of pairs of bit lines are provided with each pair connected to the cells of a respective column to select one column and thereby one cell of the selected row. Each cell preferably comprises a cross-coupled pair of transistors each having a collector and first and second emitters. The word top lines are connected to the collector load impedances, the word bottom lines are connected to the first emitters, and the bit lines are connected to the second emitters.

公开(公告)号：DE2329643A1

公开(公告)日：1974-01-24

申请号：DE2329643

申请日：1973-06-09

Applicant: IBM

Inventor： PLATT STEVEN ,  POMERANZ JEHOSHUA NAPHTALI ,  TEWARSON DINESH KUMAR

IPC: H03F3/45 ,  H03K5/003 ,  H03K19/018 ,  H03K19/082 ,  H03K5/00

Abstract: A signal voltage level translating circuit receives an input electrical signal having predetermined voltage swings about a first predetermined voltage level and translates the voltage level of the signal so that at the output there is provided an output electrical signal having the same voltage swings about a second predetermined voltage level translated with respect to the first voltage level. An input transistor has its base connected to the input node and its emitter connected to one end of a first impedance element having its other end connected to the collector of a current source transistor. A fixed reference voltage is applied to the base of a reference voltage transistor having its emitter connected to one end of a second impedance element having an impedance equal to that of the first impedance element. The other end of the second impedance element is connected to the collector of a diode-connected transistor having its base connected to the base of the current source transistor. The emitter of the diode-connected transistor is connected to the emitter of the current source transistor. If implemented in the form of a monolithic integrated circuit, the diode-connected transistor and current source transistor may have the same base and the same emitter. The translated signal is taken at the output where the first impedance element is connected to the collector of the current source transistor.