公开(公告)号：DE69025510T2

公开(公告)日：1996-09-19

申请号：DE69025510

申请日：1990-06-23

Applicant: IBM

Inventor： MINASSIAN VAHE ARPAK ,  MIRACLE GERALD HOLT ,  NEUNER RICHARD ANDREW ,  POTVIN PETER LLOYD POTVIN PETE

IPC: G06F13/38 ,  G06F5/16 ,  G06F13/12 ,  H04L13/10 ,  G06F5/06

Abstract: An asynchronous high-speed data interface for coupling a serial channel to a parallel control unit. A first state machine, running synchronously with the channel transmitter clock, controls the filling of a pair of dual-port input buffers (32) in alternating fashion with data bytes from incoming serial frames that have been deserialized and decoded. A second state machine, running synchronously with a second clock that is asynchronous with the channel transmitter clock, controls the transfer of the data bytes from the selected input buffer (32) to one of a pair of output buffers (44) en route to the control unit. Upon detecting the receipt of the third incoming data byte, the first state machine sets a start latch (74), causing the second state machine to begin transferring data from the selected input buffer to the selected output buffer while the input buffer is still being filled. Means are provided for disregarding the data bytes that have been transferred to the selected output buffer if the frame is ultimately aborted.

公开(公告)号：DE69025510D1

公开(公告)日：1996-04-04

申请号：DE69025510

申请日：1990-06-23

Applicant: IBM

Inventor： MINASSIAN VAHE ARPAK ,  MIRACLE GERALD HOLT ,  NEUNER RICHARD ANDREW ,  POTVIN PETER LLOYD POTVIN PETE

IPC: G06F13/38 ,  G06F5/16 ,  G06F13/12 ,  H04L13/10 ,  G06F5/06

Abstract: An asynchronous high-speed data interface for coupling a serial channel to a parallel control unit. A first state machine, running synchronously with the channel transmitter clock, controls the filling of a pair of dual-port input buffers (32) in alternating fashion with data bytes from incoming serial frames that have been deserialized and decoded. A second state machine, running synchronously with a second clock that is asynchronous with the channel transmitter clock, controls the transfer of the data bytes from the selected input buffer (32) to one of a pair of output buffers (44) en route to the control unit. Upon detecting the receipt of the third incoming data byte, the first state machine sets a start latch (74), causing the second state machine to begin transferring data from the selected input buffer to the selected output buffer while the input buffer is still being filled. Means are provided for disregarding the data bytes that have been transferred to the selected output buffer if the frame is ultimately aborted.