1.
    发明专利
    未知

    公开(公告)号:DE69028462T2

    公开(公告)日:1997-03-27

    申请号:DE69028462

    申请日:1990-06-23

    Applicant: IBM

    Abstract: A device control unit (19) operating under the protocol of a parallel bus (24) is connected by a serial link (18, 20) to a channel that is primarily adapted to operate under a different protocol with device control units connected by a serial link. An extender unit (22) interconnects the parallel bus (24) and the serial link (18, 20) and performs the specific operations of the parallel bus protocol. The channel and the extender unit (22) send serial frames on the link for data transfer and associated operations. These frames are constructed according to a protocol that provides an intermediate step in translating between the protocol of the serial control units and the protocol of the parallel control units. The channel is operable in either mode (by microcode) and the new protocol permits the serial channel mode to be independent of the protocol of the parallel control unit and it permits the two modes to be closely similar in many features. New operations using the protocol reduce the delays that would otherwise be required in the communications between the channel and the extender unit. The serial link (18, 20) can be made longer when the delays are reduced.

    4.
    发明专利
    未知

    公开(公告)号:DE69028462D1

    公开(公告)日:1996-10-17

    申请号:DE69028462

    申请日:1990-06-23

    Applicant: IBM

    Abstract: A device control unit (19) operating under the protocol of a parallel bus (24) is connected by a serial link (18, 20) to a channel that is primarily adapted to operate under a different protocol with device control units connected by a serial link. An extender unit (22) interconnects the parallel bus (24) and the serial link (18, 20) and performs the specific operations of the parallel bus protocol. The channel and the extender unit (22) send serial frames on the link for data transfer and associated operations. These frames are constructed according to a protocol that provides an intermediate step in translating between the protocol of the serial control units and the protocol of the parallel control units. The channel is operable in either mode (by microcode) and the new protocol permits the serial channel mode to be independent of the protocol of the parallel control unit and it permits the two modes to be closely similar in many features. New operations using the protocol reduce the delays that would otherwise be required in the communications between the channel and the extender unit. The serial link (18, 20) can be made longer when the delays are reduced.

    5.
    发明专利
    未知

    公开(公告)号:DE69025510T2

    公开(公告)日:1996-09-19

    申请号:DE69025510

    申请日:1990-06-23

    Applicant: IBM

    Abstract: An asynchronous high-speed data interface for coupling a serial channel to a parallel control unit. A first state machine, running synchronously with the channel transmitter clock, controls the filling of a pair of dual-port input buffers (32) in alternating fashion with data bytes from incoming serial frames that have been deserialized and decoded. A second state machine, running synchronously with a second clock that is asynchronous with the channel transmitter clock, controls the transfer of the data bytes from the selected input buffer (32) to one of a pair of output buffers (44) en route to the control unit. Upon detecting the receipt of the third incoming data byte, the first state machine sets a start latch (74), causing the second state machine to begin transferring data from the selected input buffer to the selected output buffer while the input buffer is still being filled. Means are provided for disregarding the data bytes that have been transferred to the selected output buffer if the frame is ultimately aborted.

    6.
    发明专利
    未知

    公开(公告)号:DE69025510D1

    公开(公告)日:1996-04-04

    申请号:DE69025510

    申请日:1990-06-23

    Applicant: IBM

    Abstract: An asynchronous high-speed data interface for coupling a serial channel to a parallel control unit. A first state machine, running synchronously with the channel transmitter clock, controls the filling of a pair of dual-port input buffers (32) in alternating fashion with data bytes from incoming serial frames that have been deserialized and decoded. A second state machine, running synchronously with a second clock that is asynchronous with the channel transmitter clock, controls the transfer of the data bytes from the selected input buffer (32) to one of a pair of output buffers (44) en route to the control unit. Upon detecting the receipt of the third incoming data byte, the first state machine sets a start latch (74), causing the second state machine to begin transferring data from the selected input buffer to the selected output buffer while the input buffer is still being filled. Means are provided for disregarding the data bytes that have been transferred to the selected output buffer if the frame is ultimately aborted.

    7.
    发明专利
    未知

    公开(公告)号:DE3678309D1

    公开(公告)日:1991-05-02

    申请号:DE3678309

    申请日:1986-01-24

    Applicant: IBM

    Abstract: @ Data is transferred between a channel (42) and a control unit (13) in interlocked mode or in data streaming mode over a conventional parallel bus and a serial link that permits the control unit and the channel to be located farther apart than the length of the parallel bus. The serial link carries frames - (30) for the rise of the data transfer tags but not their fall, and these tags on the parallel bus are dropped by two circuits that connect the serial link to the parallel bus. In data streaming mode, one data transfer tag is dropped when the next data transfer tag is received on the serial link. The circuit at the control unit end of the serial link detects a pause in the tags to begin an operation to drop the last data transfer tags and both circuits respond to other conditions to drop the last data transfer tags according to the protocol of the parallel 'bus.

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