公开(公告)号：BR7907419A

公开(公告)日：1980-08-05

申请号：BR7907419

申请日：1979-11-14

Applicant: IBM

Inventor： PRABHAKAR GOEL

IPC: G01R31/28 ,  G01R31/3183 ,  G06F11/22 ,  G06F11/30 ,  H03K19/20

Abstract: A path oriented decision making test pattern generator is embodied in a logic chip test system for testing large-scale integrated circuits having many internal nodes inaccessible to the test probes of chip testing machines. For each designated possible chip fault, consisting of a stuck-high or stuck-low voltage at a node of the chip logic network, the generator provides a test pattern of signals to be applied to the input pins of each chip, so that the resulting signal at an output pin indicates whether the fault is present in the chip.

公开(公告)号：IT1150035B

公开(公告)日：1986-12-10

申请号：IT2369180

申请日：1980-07-25

Applicant: IBM

Inventor： SUMIT DAS GUPTA ,  PRABHAKAR GOEL ,  WILLIAMS THOMAS WALTER

IPC: G06F7/00 ,  G01R31/3185 ,  G06F11/22 ,  G06F

Abstract: According to the invention, the LSI testing methods allow the states of combinational logic networks to be captured in either a group of master latches (390) or slave latches (400) of shift registers used for performing scan-in/scan-out operations on test data (test patterns, result patterns), but not both, If on a particular test the states are captured in the master latches, then each master latch state is subsequently shifted to the corresponding slave latch by the application of a shift clock, as known from the art. If instead the states are captured in the slave latches the slave latches can be immediately shifted out for inspection.