公开(公告)号：GB1038704A

公开(公告)日：1966-08-10

申请号：GB627364

申请日：1964-02-14

Applicant: IBM

Inventor： GLOVER ALAN CHARLES ,  PRATT ROBERT LAVERNE

IPC: G06F7/495 ,  G06F7/50 ,  G06F9/22 ,  G06F9/26 ,  G06F11/10 ,  G06F11/28

Abstract: 1,038,704. Error detection. INTERNATIONAL BUSINESS MACHINES CORPORATION. Sept. 14, 1964 [Feb. 14, 1964], No. 6273/64. Heading G4A. In a data store, a word comprises (a) bits for addressing the next word, (b) a check bit for the bits (a), and (c) a check bit for the address of the current word (" true address "), and the bit (b) of a word read from the store or a bit derived from it is delayed for one store cycle and then compared with the bit (c) of the next word read out to check that this latter word is the required one. The invention is applied to a read-only microprogramme store. In order to allow address modification in accordance with machine conditions, a word read from the store and placed in latches also supplies condition bits to a " condition test " unit also responsive to machine condition signals to produce signals for modifying or supplementing the address bits (a) from the word in the latches. Fig. 3 (not shown) shows the " condition test " unit as a single exclusive-or gate receiving a carry indication, and a single condition bit from the latches, and producing a bit which together with the address bits (a) from the latches constitutes the address of the next word in the store. If the bit from the " condition test " unit is ONE, the check bit (b) from the latches is inverted (details in Fig. 3, not shown) before reaching the delay.