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    Data Processing Systems
    1.
    发明专利
    Data Processing Systems 未知

    公开(公告)号：GB1163859A

    公开(公告)日：1969-09-10

    申请号：GB3442968

    申请日：1968-07-19

    Applicant: IBM

    Inventor： ARULPRAGASAM JEGANANDARAJ AMAL ,  MINSHULL JOHN FRANCIS ,  PINNELL MARTIN COXWELL ,  GLOVER ALAN CHARLES ,  TUFFILL HAROLD WILLIAM ,  WAUGH ROBIN

    IPC: G06F11/14 ,  G06F11/20

    Abstract: 1,163,859. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 19 July, 1968, No. 34429/68. Heading G4A. In a data processing system, a recovery log unit maintains a profile of a first CPU (central processing unit) updated to a time before error is detected in the first CPU, and detection of error in the first CPU causes a second CPU to process the profile into storable form and store it in common main storage. The profile is all information necessary to permit a cleared CPU to continue its programme where it left off, including information of pending interrupts. Detection of error prevents further updating of the profile, and an error which persists despite instruction retry, or power failure, causes the second CPU to process the profile as stated above. The second CPU has its own recovery log unit and is normally concerned with its own tasks, and when required to process the profile of the other CPU as above, it temporarily stores its own working section in the main storage. The second CPU may take over the tasks of the first, using the profile of the first, in which case it processes its own profile and stores it in the main storage. The first CPU can perform for the second the services which the second is described above as performing for the first, and further CPU's can be provided. A profile can be forced into the system for diagnostic purposes.

    A self-addressed data store
    4.
    发明专利
    A self-addressed data store 未知

    公开(公告)号：GB1038704A

    公开(公告)日：1966-08-10

    申请号：GB627364

    申请日：1964-02-14

    Applicant: IBM

    Inventor： GLOVER ALAN CHARLES ,  PRATT ROBERT LAVERNE

    IPC: G06F7/495 ,  G06F7/50 ,  G06F9/22 ,  G06F9/26 ,  G06F11/10 ,  G06F11/28

    Abstract: 1,038,704. Error detection. INTERNATIONAL BUSINESS MACHINES CORPORATION. Sept. 14, 1964 [Feb. 14, 1964], No. 6273/64. Heading G4A. In a data store, a word comprises (a) bits for addressing the next word, (b) a check bit for the bits (a), and (c) a check bit for the address of the current word (" true address "), and the bit (b) of a word read from the store or a bit derived from it is delayed for one store cycle and then compared with the bit (c) of the next word read out to check that this latter word is the required one. The invention is applied to a read-only microprogramme store. In order to allow address modification in accordance with machine conditions, a word read from the store and placed in latches also supplies condition bits to a " condition test " unit also responsive to machine condition signals to produce signals for modifying or supplementing the address bits (a) from the word in the latches. Fig. 3 (not shown) shows the " condition test " unit as a single exclusive-or gate receiving a carry indication, and a single condition bit from the latches, and producing a bit which together with the address bits (a) from the latches constitutes the address of the next word in the store. If the bit from the " condition test " unit is ONE, the check bit (b) from the latches is inverted (details in Fig. 3, not shown) before reaching the delay.

    Improvements in or relating to error checking devices
    6.
    发明专利
    Improvements in or relating to error checking devices 未知

    公开(公告)号：GB1041232A

    公开(公告)日：1966-09-01

    申请号：GB1526263

    申请日：1963-04-18

    Applicant: IBM

    Inventor： GLOVER ALAN CHARLES ,  PRATT ROBERT LA VERNE

    IPC: G06F11/10

    Abstract: 1,041,232. Electric digital data-storage. INTERNATIONAL BUSINESS MACHINES CORPORATION. April 6, 1964 [April 18, 1963], No. 15262/63. Heading G4C. A data memory is addressed by selecting at least one gating device, check information being generated in accordance with which device is selected and being compared with check information stored with the address in the address register. Referring to Fig. 1 (not shown) which shows means for selecting one co-ordinate of a magnetic core matrix store, one of 64 address lines is selected by selecting one of 8 left-hand gates and one of 8 right-hand gates in accordance with corresponding binary-coded addresses in an address register 1. Current passes through one of two transformers 11, 12 depending on whether the address of the selected left-hand gate has an odd or even number of 1's. Transformers 13, 14 are selected similarly with respect to the right-hand gates. The transformers 11 to 14 supply inputs as shown to an exclusive-or gate 16 via latches 31, 33, the output of gate 16 being compared at 35 with a parity bit from register 1.

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