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    3.
    发明专利
    未知

    公开(公告)号：DE1499720B1

    公开(公告)日：1970-10-22

    申请号：DE1499720

    申请日：1966-09-29

    Applicant: IBM

    Inventor： PROUDMAN ANTONY

    IPC: G11C11/40 ,  G11C11/411 ,  G11C11/414 ,  G11C11/416 ,  G11C15/04 ,  H03K3/286

    Abstract: 1,119,357. Transistor matrix stores. INTERNATIONAL BUSINESS MACHINES CORP. 7 Oct., 1965, No. 42540/65. Heading G4C. [Also in Division H3] Binary storage elements in a matrix store comprise two cross coupled transistors. If the read-out pulse is applied to the word line of the element shown in Fig. 11 it passes through a transistor T2 to the bit line only when transistor T2 of a bi-stable circuit T1, T2 is conducting. Non-destructive read out is thus achieved. Similarly it would pass to a bit line connected to T1 only if T1 is conducting. The circuit may be set to one or other states by pulses applied to the appropriate one of the " write zero " or " write one " terminals or alternatively it may be set by applying a small positive or negative pulse to the bit line, according to whether a zero or one is to be recorded, and lowering the potential of the word line so that setting is effected when the word line is returned to its operating potential. The circuit may be re-arranged so that the bit line is connected to one collector lead and the word line is connected to the emitters in common (Fig. 4, not shown). Alternatively a Schmidt trigger may be used with the word line connected to the collectors and the bit line to the common emitter resistor, one of the bases being connected to earth so that an interrogate pulse on the word line will pass through the other transistor but not through the earthed base transistor (Fig. 5, not shown). Information can be transferred from one memory plane to another through output transistors connected as illustrated in Fig. 9 (not shown). Logic operations may be effected in transferring information from one element in a plane to another (Fig. 6, not shown). To transfer the complement from one element A to another B a half current negative bias pulse is applied to a bit line common to the elements and an interrogate pulse to the word line of A. Word line B is taken to earth potential or below and is returned before the interrogate and bias signals are removed. To transfer the true signal, negative interrogate and positive bias current is used. The logic operation A.B may be transferred to B by interrogating A with a 5 volts signal and applying a conditional reset signal of 0À9 volt to word line B. It is explained that with the normal word line potential of + 1À5 volts and T2 conducting the change over is determined by the point at which T2 is unable to hold off T1 but with the word line potential at +0À9 volt the change over is determined by the point at which T2 is unable to remain on because of reduction of base current. The logic A.B is transferred to B by interrogating A with a negative wave and applying a positive bias to the bit line. Appropriate wave forms are illustrated in Figs. 7 and 8 (not shown). An interrogate signal can also be applied to a bit line and the state detected by sense amplifiers in the word line and this is useful for detecting miss-matches in an associative store.

    Data store
    4.
    发明专利
    Data store 未知

    公开(公告)号：GB1055601A

    公开(公告)日：1967-01-18

    申请号：GB1310265

    申请日：1965-03-27

    Applicant: IBM

    Inventor： HOBBIS ALLAN JAMES ,  PROUDMAN ANTONY

    IPC: G11C13/04 ,  H01L27/144

    Abstract: 1,055,601. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORPORATION. March 27, 1965, No. 13102/65. Heading H1K. A data store comprises a semi-condnctor block providing a matrix of light sensitive devices, each comprising a small region of opposite conductivity type; the small regions are connected in columns 2-9 each with an input terminal and a plurality of light sources 10-17 are arranged each to direct light towards a respective row; any one device may then be selected by energizing one of the input terminals and one of the light sources to provide an output from the common output terminal 18. Information may be stored by providing apertured masks in the light path so that light is allowed to reach only selected ones of the devices in each row. The light paths may be provided by light rods with reflecting notches or optical fibres and the semi-conductor block may be phosphorus doped silicon with boron diffused islands. The light sources may consist of lasers or gallium arsenide diodes and a plurality of semiconductor blocks in different planes may be provided. Transistors may be used in place of diodes, the connections being made to the emitters and the bases being disconnected so that the transistors operate as diodes.

    5.
    发明专利
    未知

    公开(公告)号：DE1261168B

    公开(公告)日：1968-02-15

    申请号：DEJ0024004

    申请日：1963-07-04

    Applicant: IBM

    Inventor： OWEN CHARLES EDWARD ,  PROUDMAN ANTONY

    IPC: G11C17/04 ,  G11C11/24

    Abstract: 1,055,261. Read-only stores. INTERNATIONAL BUSINESS MACHINES CORPORATION. July 4, 1963 [July 10, 1962]. No. 26504/62. Heading G4A. In read-only memories in which a capacitive or other connection is made between selected drive and sense lines from sets of such lines the invention provides that there is a constant impedance to current in the drive line whatever the form of the stored data. This is done in Fig. 2 (not shown) by providing pairs of sense lines both lines of a pair being connected to a differential amplifier. One bits are stored by connecting the lines S1a, S2a to appropriate drive lines, and zero bits by connecting the lines S1b, S2b to the drive lines. Fig. 3 (not shown) shows pairs of drive and sense lines. Ones are stored by connecting the d drive lines to the p sense lines and the b drive lines to the q sense lines and zeroes by making the opposite connections. To pulse a drive line a transistor from the set G1 to GN is sent conductive after which a transistor T1 or T2 . . . is pulsed. The invention is also applicable to inductive readonly stores.

    Improvements in or relating to information stores
    6.
    发明专利
    Improvements in or relating to information stores 未知

    公开(公告)号：GB985347A

    公开(公告)日：1965-03-10

    申请号：GB4652262

    申请日：1962-12-10

    Applicant: IBM

    Inventor： WARWICK WILLIAM ARTHUR ,  BOLTON IVOR WILLIAM ,  GOWER KENNETH NORTHCOTT ,  OWEN CHARLES EDWARD ,  PROUDMAN ANTONY ,  TAUB DANIEL MATTHEW

    IPC: G11C17/02 ,  H01R12/70

    Abstract: 985, 347. Permanent data stores. INTERNATIONAL BUSINESS MACHINES CORPORATION. Aug. 28, 1963 [Dec. 10, 1962], No. 46522/62. Heading G4A. [Also in Divisions H1 and H2] A permanent data store comprises a plurality of elongated insulating carriers each having a plurality of apertures spaced along its length in at least one row, the carriers being stacked with corresponding apertures in registration; a plurality of transformer cores passing through the registering apertures, each core having an associated sensing winding; and drive conductors for each row extending continuously along the length of each carrier and passing to one side or the other of each aperture so as to thread or not to thread the associated transformer core, in accordance with the data stored. The permanent store described comprises a stack of 128 flexible tapes 15, Fig. 6, made of in-. sulating material and having two rows 16, 17 of sixty apertures, rectangular transformer cores each comprising a U-shaped part 13 and a straight I-shaped part 14 passing through each pair of corresponding apertures. With each row of apertures is associated on each tape a corresponding drive winding 18 or 21, formed by deposition on the tape and threading or not threading the transformer cores according as a binary "1" or "0" is stored, each row being regarded as storing a 60- bit binary data "word" which may be read out by applying a pulse to the required winding 18 or 21 to produce output signals on the transformer secondaries 19 only where a "1" is stored. Tape fabrication. Each tape after punching with the transformer core apertures 16, 17 has deposited thereon conductive ladder networks 24, 25, Fig. 7, the unwanted portions of the networks 24, 25 being removed by punching (Fig. 8 no shown), etching or abrading (Fig. 9 not shown). As shown in Fig. 41, a copper clad polyester tape 135 is cleaned at 137, a layer of photo-resist material being applied which is then dried and an exposure made of the required continuous ladder networks. The tape is then passed through an etching bath 140, the unwanted photo-resist material being removed at 141. The required data may be punched on the tape from a program stored on punched cards (Fig. 42, not shown). Tape arrangements. In practice, each tape is punched with four rows of thirty apertures each, Fig. 10, the two outer rows being connected by a conductor 51 to form a first 60-bit stored word and the two inner rows being connected at 52 to form a second 60-bit word, the four input/output connections thus being available at one end of the tape on an extension 53. The stack of 128 tapes is arranged in two halves of 64 tapes, the two halves being in inverted relationship, Fig. 14 with an additional insulating tape (not shown) separating the two halves. Reducing inter-tape coupling. Due to the proximity of the tapes to one another undesired inter-tape capacitative and inductive coupling may result in damped oscillations or ringing in the selected winding. This effect may be reduced in three ways. Firstly, each transformer core may carry a short-circuit winding in the form of a damping resistor, these resistors being formed as loops 78, Fig. 22, on an additional insulating tape 76, one or more of such tapes being arranged in the tape store stack. Secondly, with each transformer core S, Fig. 23, may be associated an additional core T, the drive winding being wound similarly through the associated cores S, T, the core T being made of a lossy material or having resistive loops as described above. Thirdly, there may be three types of storage tapes (Figs. 24 to 26, not shown), used in turn in the tape stack and having their core apertures displaced by different amounts with respect to the centres of the ladder network elements so that when the tapes are positioned with the apertures aligned, the conductive drive windings in adjacent tapes are relatively displaced. Tape module construction. The tape stack of 128 tapes is mounted in an assembly comprising end blocks 82, 83, Fig. 27 spaced apart by rods 84. Into the blocks 82, 83 are screwed aligning pins 86 on which the tapes 39 are mounted and on the rods 84 are mounted the transformer core carrier assemblies 88, shown in detail in Fig. 31. Each core carrier assembly 88 comprises slots 92 for the I-shaped parts 14 of two cores, the four ends of two U-shaped parts 13 passing through holes in the assembly 88 to contact the I-shaped parts which are retained in position by leaf springs 96 cooperating with a retainer 94 which slides into retaining position and has contact pins 97 for making connections to the transformer secondaries which are wound in grooves 98 on the assembly 88 and not on the I-shaped parts themselves. An insulating sheet 98 Fig. 27, is placed over the closed ends of the U-shaped parts and is retained in position by brackets 99, 100, 101. The tape extension leads 53 are fanned out and plugged into one of two module boards 105, where the plugs on the tape connected to the word drive windings can be soldered in position in holes in the boards. Each board 105, Fig. 33 has a first group of four 32-hole columns 107, 108, 109, 111 and a second such group 112, 113, 114, 115, there being a central column 116 of 32 holes. The first two holes in the column 116 are connected respectively by leads 117, 118 to all the holes in the respective columns 109, 111, the last two holes being similarly connected to the columns 114, 115 and the remaining holes in the column 116 are connected each to the corresponding holes in the columns 107, 108, 112, 113 via diodes 121, the connections being illustrated in Fig. 34 (not shown). Thus selection of one of the 32 intermediate holes in the column 116 together with selection of one of the four end holes will select a particular word drive winding on a particular tape. The holes 2 in the column 116 co-operate with plugs on a connector cable (Fig. 35, not shown) for addressing the store. A total of sixteen modules may be arranged to form a large capacity permanent store (Fig. 36, not shown), the selection circuits comprising transistors (Figs. 37-40, not shown).

    A data store
    9.
    发明专利
    A data store 未知

    公开(公告)号：GB1119357A

    公开(公告)日：1968-07-10

    申请号：GB4254065

    申请日：1965-10-07

    Applicant: IBM

    Inventor： PROUDMAN ANTONY

    IPC: G11C11/40 ,  G11C11/411 ,  G11C11/414 ,  G11C11/416 ,  G11C15/04 ,  H03K3/286

    Abstract: 1,119,357. Transistor matrix stores. INTERNATIONAL BUSINESS MACHINES CORP. 7 Oct., 1965, No. 42540/65. Heading G4C. [Also in Division H3] Binary storage elements in a matrix store comprise two cross coupled transistors. If the read-out pulse is applied to the word line of the element shown in Fig. 11 it passes through a transistor T2 to the bit line only when transistor T2 of a bi-stable circuit T1, T2 is conducting. Non-destructive read out is thus achieved. Similarly it would pass to a bit line connected to T1 only if T1 is conducting. The circuit may be set to one or other states by pulses applied to the appropriate one of the " write zero " or " write one " terminals or alternatively it may be set by applying a small positive or negative pulse to the bit line, according to whether a zero or one is to be recorded, and lowering the potential of the word line so that setting is effected when the word line is returned to its operating potential. The circuit may be re-arranged so that the bit line is connected to one collector lead and the word line is connected to the emitters in common (Fig. 4, not shown). Alternatively a Schmidt trigger may be used with the word line connected to the collectors and the bit line to the common emitter resistor, one of the bases being connected to earth so that an interrogate pulse on the word line will pass through the other transistor but not through the earthed base transistor (Fig. 5, not shown). Information can be transferred from one memory plane to another through output transistors connected as illustrated in Fig. 9 (not shown). Logic operations may be effected in transferring information from one element in a plane to another (Fig. 6, not shown). To transfer the complement from one element A to another B a half current negative bias pulse is applied to a bit line common to the elements and an interrogate pulse to the word line of A. Word line B is taken to earth potential or below and is returned before the interrogate and bias signals are removed. To transfer the true signal, negative interrogate and positive bias current is used. The logic operation A.B may be transferred to B by interrogating A with a 5 volts signal and applying a conditional reset signal of 0À9 volt to word line B. It is explained that with the normal word line potential of + 1À5 volts and T2 conducting the change over is determined by the point at which T2 is unable to hold off T1 but with the word line potential at +0À9 volt the change over is determined by the point at which T2 is unable to remain on because of reduction of base current. The logic A.B is transferred to B by interrogating A with a negative wave and applying a positive bias to the bit line. Appropriate wave forms are illustrated in Figs. 7 and 8 (not shown). An interrogate signal can also be applied to a bit line and the state detected by sense amplifiers in the word line and this is useful for detecting miss-matches in an associative store.

    10.
    发明专利
    未知

    公开(公告)号：FR1494394A

    公开(公告)日：1967-09-08

    申请号：FR06008023

    申请日：1966-09-12

    Applicant: IBM

    Inventor： PROUDMAN ANTONY

    IPC: G11C11/40 ,  G11C11/411 ,  G11C11/414 ,  G11C11/416 ,  G11C15/04 ,  H03K3/286

    Abstract: 1,119,357. Transistor matrix stores. INTERNATIONAL BUSINESS MACHINES CORP. 7 Oct., 1965, No. 42540/65. Heading G4C. [Also in Division H3] Binary storage elements in a matrix store comprise two cross coupled transistors. If the read-out pulse is applied to the word line of the element shown in Fig. 11 it passes through a transistor T2 to the bit line only when transistor T2 of a bi-stable circuit T1, T2 is conducting. Non-destructive read out is thus achieved. Similarly it would pass to a bit line connected to T1 only if T1 is conducting. The circuit may be set to one or other states by pulses applied to the appropriate one of the " write zero " or " write one " terminals or alternatively it may be set by applying a small positive or negative pulse to the bit line, according to whether a zero or one is to be recorded, and lowering the potential of the word line so that setting is effected when the word line is returned to its operating potential. The circuit may be re-arranged so that the bit line is connected to one collector lead and the word line is connected to the emitters in common (Fig. 4, not shown). Alternatively a Schmidt trigger may be used with the word line connected to the collectors and the bit line to the common emitter resistor, one of the bases being connected to earth so that an interrogate pulse on the word line will pass through the other transistor but not through the earthed base transistor (Fig. 5, not shown). Information can be transferred from one memory plane to another through output transistors connected as illustrated in Fig. 9 (not shown). Logic operations may be effected in transferring information from one element in a plane to another (Fig. 6, not shown). To transfer the complement from one element A to another B a half current negative bias pulse is applied to a bit line common to the elements and an interrogate pulse to the word line of A. Word line B is taken to earth potential or below and is returned before the interrogate and bias signals are removed. To transfer the true signal, negative interrogate and positive bias current is used. The logic operation A.B may be transferred to B by interrogating A with a 5 volts signal and applying a conditional reset signal of 0À9 volt to word line B. It is explained that with the normal word line potential of + 1À5 volts and T2 conducting the change over is determined by the point at which T2 is unable to hold off T1 but with the word line potential at +0À9 volt the change over is determined by the point at which T2 is unable to remain on because of reduction of base current. The logic A.B is transferred to B by interrogating A with a negative wave and applying a positive bias to the bit line. Appropriate wave forms are illustrated in Figs. 7 and 8 (not shown). An interrogate signal can also be applied to a bit line and the state detected by sense amplifiers in the word line and this is useful for detecting miss-matches in an associative store.

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