公开(公告)号：CA1143855A

公开(公告)日：1983-03-29

申请号：CA360339

申请日：1980-09-16

Applicant: IBM

Inventor： HARDIN DICK K ,  PUTTLITZ FREDERIC J

IPC: G06F15/16 ,  G06F12/00 ,  G06F13/18 ,  G06F15/177 ,  G06F13/00

Abstract: A system is provided that includes a plurality of processors connected to a shared storage via an asynchronous storage interface that includes various interface logic and a ring counter that performs polling of the processors for access to the shared storage. The ring utilizes a "lookahead" feature that bypasses stages in the ring to speed up responses to request signals from the processor. The logic uses the clock from the particular processor accessing the shared memory at any point in time. BC9-78-026

公开(公告)号：CA1078070A

公开(公告)日：1980-05-20

申请号：CA275574

申请日：1977-04-05

Applicant: IBM

Inventor： BOURKE DONALL G ,  PUTTLITZ FREDERIC J

IPC: G06F12/14 ,  G06F9/34 ,  G06F12/02 ,  G06F12/06 ,  G06F13/00

Abstract: Extending the size of the main memory of a data processing system having a synchronous inner storage unit by attaching a relocation translator having special connection interfaces and translated addressing for attaching a synchronous outer storage unit and an asynchronous storage unit which may be remotely located from the processor. A different form of storage cycle is generated by the translator for interfacing each of the three storage units being accessed. The translator performs address translation which expands the number of bits in the physical address to support the extended main memory. The extended address uses a concatenation of a program-derived address and a machinederived address key. The maximum extendable size of the memory can substantially exceed the maximum addressing capability of any program, which is determined by the relocatable addressability obtained through any stack of segmentation registers. The maximum extendable size of the main memory is determined by the number of bit positions in the physical block address field in a segmentation register (for addressing a physical block in any of the storage units) concatenated with the number of bit positions needed to address a location in any selected storage block.

公开(公告)号：FR2349888A1

公开(公告)日：1977-11-25

申请号：FR7706858

申请日：1977-03-02

Applicant: IBM

Inventor： BOURKE DONALL G ,  PUTTLITZ FREDERIC J

IPC: G06F12/14 ,  G06F9/34 ,  G06F12/02 ,  G06F12/06 ,  G06F13/00

Abstract: Extending the size of the main memory of a data processing system having a synchronous inner storage unit by attaching a relocation translator having special connection interfaces and translated addressing for attaching a synchronous outer storage unit and an asynchronous storage unit which may be remotely located from the processor. A differnt form of storage cycle is generated by the translator for interfacing each of the three storage units being accessed. The translator performs address translation which expands the number of bits in the physical address to support the extended main memory. The extended address uses a concatenation of a program-derived address and a machine-derived address key.